公开(公告)号：WO2021021946A1

公开(公告)日：2021-02-04

申请号：PCT/US2020/044091

申请日：2020-07-29

Applicant: XILINX, INC.

Inventor： POPE, Steven L. ,  RIDDOCH, David J. ,  ROBERTS, Derek ,  KITARIEV, Dmitri ,  TURTON, Neil

IPC: G06F13/40 ,  G06F13/28 ,  G06F13/12 ,  G06F13/42 ,  G06F13/38 ,  G06F12/0802

Abstract: A network interface device (102) comprises a programmable interface (119) configured to provide a device interface with at least one bus between the network interface device (102) and a host device (101). The programmable interface (119) is programmable to support a plurality of different types of a device interface.

公开(公告)号：WO2020094664A1

公开(公告)日：2020-05-14

申请号：PCT/EP2019/080281

申请日：2019-11-05

Applicant: XILINX, INC. ,  POPE, Steven

Inventor： POPE, Steven ,  TURTON, Neil ,  RIDDOCH, David ,  KITARIEV, Dmitri ,  SOHAN, Ripduman ,  ROBERTS, Derek

IPC: G06F9/50 ,  H04L12/933

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：WO2022192048A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/018540

申请日：2022-03-02

Applicant: XILINX, INC.

Inventor： POPE, Steven Leslie ,  ROBERTS, Derek Edward ,  KITARIEV, Dmitri ,  TURTON, Neil Duncan ,  RIDDOCH, David James ,  SOHAN, Ripduman

IPC: G06F3/06

Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.

公开(公告)号：WO2022192071A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/018783

申请日：2022-03-03

Applicant: XILINX, INC.

Inventor： POPE, Steven Leslie ,  ROBERTS, Derek Edward ,  KITARIEV, Dmitri ,  TURTON, Neil Duncan ,  RIDDOCH, David James ,  SOHAN, Ripduman

IPC: H04L47/10

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：WO2022271267A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/026385

申请日：2022-04-26

Applicant: XILINX, INC.

Inventor： POPE, Steven Leslie ,  ROBERTS, Derek Edward ,  KITARIEV, Dmitri ,  TURTON, Neil Duncan ,  RIDDOCH, David James ,  SOHAN, Ripduman

IPC: G06F13/16 ,  G06F13/1621 ,  G06F13/1642 ,  G06F13/1678 ,  G06F13/287 ,  G06F13/385 ,  G06F2213/3808 ,  G11C7/1069 ,  G11C7/1096

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

公开(公告)号：WO2022192094A1

公开(公告)日：2022-09-15

申请号：PCT/US2022/019029

申请日：2022-03-04

Applicant: XILINX, INC.

Inventor： POPE, Steven Leslie ,  ROBERTS, Derek Edward ,  KITARIEV, Dmitri ,  TURTON, Neil Duncan ,  RIDDOCH, David James ,  SOHAN, Ripduman

IPC: G06F9/50 ,  G06F9/54

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.