公开(公告)号：WO2022031688A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/044320

申请日：2021-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： HELM, Mark A. ,  PAWLOWSKI, Joseph T.

IPC: G06F3/06 ,  G06F12/14 ,  G06F16/903 ,  G11C16/12 ,  G11C16/24 ,  G11C7/1084

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

公开(公告)号：WO2022015741A1

公开(公告)日：2022-01-20

申请号：PCT/US2021/041445

申请日：2021-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LIMAYE, Aparna U. ,  HOLLIS, Timothy Mowry

IPC: G11C5/04 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C5/025 ,  G11C5/066 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1084 ,  G11C7/109

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.

公开(公告)号：WO2022240591A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/026719

申请日：2022-04-28

Applicant: QUALCOMM INCORPORATED

Inventor： RASMUS, Todd Morgan

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/10 ,  H03K5/24 ,  H03M9/00 ,  H04L25/02 ,  G11C2207/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1084 ,  H03K5/2481 ,  H03K5/249

Abstract: A regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, wherein a gate of the first transistor is configured to receive a first input signal, and a second transistor coupled to the input of the first inverting circuit, wherein a gate of the second transistor is configured to receive a second input signal. The regeneration circuit also includes a first switch coupled between the first transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal, and a second switch coupled between the second transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.