公开(公告)号：WO2022010728A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040060

申请日：2021-07-01

Applicant: INFINEON TECHNOLOGIES LLC

Inventor： SHLOMO, Oren

IPC: G06F21/71 ,  G06F21/76 ,  G01K7/183 ,  G01K7/20 ,  G01R19/2506 ,  G05F1/648 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/14 ,  G11C7/20 ,  H03K17/223 ,  H03K17/24 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  H03K5/2472

Abstract: A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

公开(公告)号：WO2022010754A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040222

申请日：2021-07-02

Applicant: INFINEON TECHNOLOGIES LLC

Inventor： GEYARI, Eran ,  SHLOMO, Oren ,  SOFER, Yair ,  HARUSH, Avri

IPC: H03K17/22 ,  G11C29/08 ,  H03K3/02 ,  H03K3/37 ,  H03K17/284 ,  H03L7/00 ,  G01K7/183 ,  G01K7/20 ,  G01R19/2506 ,  G05F1/648 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/14 ,  G11C7/20 ,  H03K17/223 ,  H03K17/24 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  H03K5/2472

Abstract: A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global- reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

公开(公告)号：WO2022005820A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/038507

申请日：2021-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MATSUBARA, Yasushi ,  JONO, Yusuke ,  MORGAN, Donald, Martin ,  YAMAMOTO, Nobuo

IPC: G11C11/22 ,  G11C7/06 ,  G11C11/2273 ,  G11C11/2275 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C7/065 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/20

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

公开(公告)号：WO2022015741A1

公开(公告)日：2022-01-20

申请号：PCT/US2021/041445

申请日：2021-07-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LIMAYE, Aparna U. ,  HOLLIS, Timothy Mowry

IPC: G11C5/04 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C5/025 ,  G11C5/066 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/1084 ,  G11C7/109

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. Example memory devices, systems and methods include a multiplexer circuit to further facilitate use of slower, and wider bandwidth memory devices. Devices and methods described may be configured to substantially match the capacity of a narrower, higher speed host interface.

公开(公告)号：WO2022010827A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/040419

申请日：2021-07-06

Applicant: INFINEON TECHNOLOGIES LLC

Inventor： SHLOMO, Oren

IPC: H03M1/66 ,  H03M1/74 ,  H03M1/76 ,  H03M1/78 ,  H03M1/80 ,  G01K7/183 ,  G01K7/20 ,  G01R19/2506 ,  G05F1/648 ,  G11C7/02 ,  G11C7/1039 ,  G11C7/14 ,  G11C7/20 ,  H03K17/223 ,  H03K17/24 ,  H03K5/1252 ,  H03K5/153 ,  H03K5/19 ,  H03K5/2472

Abstract: A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n-1, and the third number is 1, the total number of resistors is 2n.