公开(公告)号：WO1990004288A1

公开(公告)日：1990-04-19

申请号：PCT/US1988003461

申请日：1988-10-05

Applicant: HOWE TECHNOLOGIES CORPORATION

Inventor： HOWE TECHNOLOGIES CORPORATION ,  LALETIN, William, H.

IPC: H03K05/22

CPC classification number: H04S1/002 ,  H04B1/1646 ,  H04S7/302

Abstract: A time delay corrector derives a correction signal (30) that corrects the relative time delay or phase error (34) between two signals, for example, stereo audio signals. A window of no correction (154) is established between two threshold levels. So long as a signal representative of the relative phase error (34) on a relatively fast integration basis (82) and (84) does not logically exceed the thresholds which define this window, no rapid phase error or time delay correction is accomplished. The window of zero correction (154) thereby prevents any time delay or phase error corrections which might otherwise result from the normal phase flucutations inherent in the two correlated stereo signals, thereby preserving the stereo imaging and information content of those signals. Upon the occurrence of the need for a relatively major time delay error correction, such as that which originates with tape splices and the like, detection signals logically exceed the thresholds of the window and a phase correction is rapidly attained.

公开(公告)号：WO1986007218A1

公开(公告)日：1986-12-04

申请号：PCT/US1986001197

申请日：1986-05-30

Applicant: COULTER ELECTRONICS, LTD. ,  DUNSTAN, Harvey, J. ,  HARFIELD, John, G. ,  KNIGHT, Paul ,  PODGORNEY, Harvey, J.

Inventor： COULTER ELECTRONICS, LTD.

IPC: H03K05/22

CPC classification number: G01R29/02 ,  G01N15/1227 ,  G01R19/04 ,  G01R29/0273 ,  H03K5/1532

Abstract: Particle produced pulses (10, 12, 14) are evaluated on an individual basis for shape symmetry, with significantly asymmetric pulses, becoming subject to editing, i.e. exclusion. Pulse symmetry is determined by measuring the areas (A, B) under the pulse before and after the first pulse before and after the first pulse amplitude peak (16, 20, 24) and then by comparing those pulse areas with respect to pre-established limits which are not based upon any of the pulses then being evaluted.

Abstract translation: 颗粒产生脉冲（10,12,14）在形状对称性的个别基础上进行评估，具有明显不对称的脉冲，变得受到编辑，即排除。 通过测量在第一脉冲幅度峰值（16,20,24）之前和之后的第一脉冲之前和之后的脉冲下的区域（A，B），然后通过比较这些脉冲区域相对于预先确定的脉冲对称性 这些限制不是基于任何被评估的脉冲。

公开(公告)号：WO1998020610A1

公开(公告)日：1998-05-14

申请号：PCT/US1997016444

申请日：1997-09-15

Applicant: BURR-BROWN CORPORATION

Inventor： BURR-BROWN CORPORATION ,  WU, Michael, A.

IPC: H03K05/22

CPC classification number: H03F3/45475 ,  H03F3/303 ,  H03F3/3059 ,  H03F3/45183 ,  H03F3/4521 ,  H03F2203/45462 ,  H03F2203/45478 ,  H03F2203/45508 ,  H03F2203/45696 ,  H03F2203/45702

Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4). The bias current in the error amplifier and the resistances of first (R2) and second (R3) resistive load devices of the error amplifier are scaled to produce a drive voltage which applies a gate-to-source quiescent bias voltage to a P-channel pull-up MOSFET (M11) which is substantially equal to and tracks with the gate-to-source voltage of the reference MOSFET (M1).

Abstract translation: 操作包括差分误差放大器（3）的CMOS输出电路，以通过使等于P沟道参考MOSFET（M1）的阈值电压除以电阻的第一电流除以输出MOSFET的电阻来提供稳定的静态偏置电流 一个流过N沟道电流镜控制MOSFET（M4）的参考电阻（R1）。 具有耦合到N沟道电流镜控制MOSFET（M4）的栅极的栅极和耦合到P沟道参考MOSFET（M1）的漏极的漏极的第一N沟道电流镜输出MOSFET（M6）使得 第二电流与流过P沟道参考MOSFET（M1）的第一电流成比例。 响应于来自P沟道参考MOSFET（M1）的反馈来控制第一电流。 响应于N沟道电流镜控制MOSFET（M4）来控制误差放大器（3）中的偏置电流。 误差放大器中的偏置电流和误差放大器的第一（R2）和第二（R3）电阻负载器件的电阻被缩放以产生驱动电压，该驱动电压将栅极至源极静态偏置电压施加到P沟道 上拉MOSFET（M11），其基本上等于并跟踪参考MOSFET（M1）的栅极 - 源极电压。

公开(公告)号：WO1997028601A1

公开(公告)日：1997-08-07

申请号：PCT/US1996010673

申请日：1996-06-20

Applicant: ANALOG DEVICES, INC. (ADI)

Inventor： ANALOG DEVICES, INC. (ADI) ,  CROOK, David, T. ,  STROUD, Ernest, T.

IPC: H03K05/22

CPC classification number: H03K5/2481 ,  H03K5/003 ,  H03K17/162

Abstract: A drive circuit and method for shaping a pair of complementary digital signals into signals that drive a conventional CMOS switch (110, 112) are presented. The method adjusts the digital signals' duty cycles to set their cross point voltage levels so that at the cross points the voltage level at the CMOS switch's reference node (30) is undisturbed with respect to its fully switched level. The drive circuit includes two pairs of diodes connected PMOS load transistors (80, 82) and NMOS load transistors (98, 100), with each pair connected to a respective output terminal (94 or 96) and a respective CMSO switch (110 or 112). The CMOS transistors' channel geometries and the amount of signal current are selected to set the duty cycle of the shaped digital signals and thereby set the optimum cross point voltage levels.

Abstract translation: 提出了用于将一对互补数字信号整形成驱动常规CMOS开关（110,112）的信号的驱动电路和方法。 该方法调整数字信号的占空比以设置其交叉点电压电平，使得在交叉点，CMOS开关参考节点（30）处的电压电平相对于其完全开关电平不受干扰。 驱动电路包括连接PMOS负载晶体管（80,82）和NMOS负载晶体管（98,100）的两对二极管，每对耦合到相应的输出端子（94或96）和相应的CMSO开关（110或112） ）。 选择CMOS晶体管的通道几何形状和信号电流量来设置成形数字信号的占空比，从而设置最佳的交叉点电压电平。

公开(公告)号：WO1997014215A2

公开(公告)日：1997-04-17

申请号：PCT/IB1996001040

申请日：1996-10-03

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  BEHBAHANI, Farbod ,  FOTOWAT-AHMADY, Ali ,  NAVID, Nasrollah, S.

IPC: H03K05/22

CPC classification number: H03K5/2445 ,  H03K5/2418

Abstract: A comparator has a simple high frequency signal path from input to output formed by two differentially connected transistors (Q1, Q2) with an output transistor (Q8, Q3) connected to each. A current control circuit maintains a constant total current flowing through the differentially connected transistors (Q1, Q2). The ratio of currents flowing through the differentially connected transistors (Q1, Q2) is initially set by a control circuit (I1, I2), so that the output of the comparator is predictable when powered up. The control circuit then gradually releases control, so that there is a smooth transfer to control by a reference signal input to the comparator.

Abstract translation: 比较器具有从由两个差分连接的晶体管（Q1，Q2）形成的从输入到输出的简单的高频信号路径，其中每个连接有输出晶体管（Q8，Q3）。 电流控制电路保持流过差分连接的晶体管（Q1，Q2）的恒定总电流。 流过差分连接的晶体管（Q1，Q2）的电流的比率最初由控制电路（I1，I2）设置，使得比较器的输出在加电时是可预测的。 然后，控制电路逐渐释放控制，使得通过输入到比较器的参考信号进行平滑传输到控制。