公开(公告)号：WO1993026093A1

公开(公告)日：1993-12-23

申请号：PCT/JP1993000800

申请日：1993-06-15

Applicant: ADVANTEST CORPORATION ,  KAWABATA, Masayuki

Inventor： ADVANTEST CORPORATION

IPC: H03M01/12

CPC classification number: H03M3/00 ,  G06J1/00

Abstract: In order to implement high resolution A/D (or D/A) conversion, the differentiated waveform of an analogue (or digital) waveform signal is generated by a differentiated waveform generating unit (10). The differentiated waveform is cyclically distributed at the timings of clock signals (CK0) to integrators (141 to 14N) (N is an integer of 2 or more). These integrated outputs are converted into digital (or analogue) signals by converters (151 to 15N). These converted outputs are added by an adder (16). The added result is output as a digital (or analogue) waveform signal.

Abstract translation: 为了实现高分辨率A / D（或D / A）转换，模拟（或数字）波形信号的微分波形由微分波形生成单元（10）产生。 差分波形在时钟信号（CK0）到积分器（141〜14N）（N为2以上的整数）的定时循环分布。 这些集成输出通过转换器（151至15N）转换为数字（或模拟）信号。 这些转换的输出由加法器（16）相加。 相加的结果作为数字（或模拟）波形信号输出。

公开(公告)号：WO1996002087A1

公开(公告)日：1996-01-25

申请号：PCT/IB1995000519

申请日：1995-06-27

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  VENES, Arnoldus, Gerardus, Wilhelmus ,  NAUTA, Bram

IPC: H03M01/12

CPC classification number: H03M1/205 ,  H03M1/141

Abstract: A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTAi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (Tbi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and a dummy structure comprising a first current source, a first dummy transistor (DTA) having a control electrode coupled to the input terminal (IT), a first main electrode connected to the first current source and a second main electrode coupled to one of the first (SNa) and second (SNb) summing nodes, a second current source, and a second dummy transistor having a control electrode coupled to a bias voltage terminal (BT), a first main electrode connected to the second current source and a second main electrode coupled to the other of the first (SNa) and second (SNb) summing nodes. The dummy structure reduces capacitive error currents in the differential output current which flows in the summing nodes of the folding stage by providing cancelling currents to the summing nodes.

Abstract translation: 一种用于折叠模数转换器的折叠台（FB），所述折叠台（FB）包括：参考装置，具有用于提供上升的不同参考电压的多个连续参考端（RT1..RT11） 第一求和节点（SNa），第二求和节点（SNb）和第一输出节点（ONa）; 多个差分耦合晶体管对（TAi / TBi），每对中的每一对包括具有主电流路径的第一晶体管（TAi）和耦合到输入端（IT）的控制电极，用于接收输入电压 被折叠的第二晶体管（TBi）和具有主电流路径的第二晶体管（TBi）和耦合到所述连续参考端子的相应一个（RTAi）的控制电极，所述连续晶体管对的第一晶体管（TAi）的主电流路径为 交替地耦合到第一求和节点（SNa）和第二求和节点（SNb），并且相关联的第二晶体管（Tbi）的主电流路径被交替地耦合到第二求和节点（SNb）和第一求和节点（SNa ）; 以及包括第一电流源，具有耦合到所述输入端（IT）的控制电极的第一虚拟晶体管（DTA））的虚拟结构，连接到所述第一电流源的第一主电极和耦合到所述第一电流源 第一（SNa）和第二（SNb）求和节点，第二电流源和具有耦合到偏置电压端子（BT）的控制电极的第二虚拟晶体管，连接到第二电流源的第一主电极和第二主电极 电极耦合到第一（SNa）和第二（SNb）求和节点中的另一个。 虚拟结构通过向求和节点提供消除电流来减少在折叠级的求和节点中流动的差分输出电流中的电容性误差电流。

公开(公告)号：WO1994021049A1

公开(公告)日：1994-09-15

申请号：PCT/US1994001813

申请日：1994-02-18

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  KOTZIN, Michael, D. ,  SCHULER, Joseph

IPC: H03M01/12

CPC classification number: H03M1/121

Abstract: A method and apparatus are provided for digitizing a wide frequency bandwidth signal (105). The digitizing is accomplished by separating the wide frequency bandwidth signal (105) into a plurality of narrow frequency bandwidth signals with a plurality of filters (110). Subsequently, a converter (120) generates digitized samples of the narrow frequency bandwidth signals. Finally, a composite digitized signal (160) is generated by a combiner (150) from the digitized samples which substantially represents the wide frequency bandwidth signal (105).

Abstract translation: 提供了一种用于数字化宽频带信号（105）的方法和装置。 通过用多个滤波器（110）将宽频带宽信号（105）分离成多个窄频带宽信号来实现数字化。 随后，转换器（120）产生窄频带宽信号的数字化采样。 最后，合成数字化信号（160）由组合器（150）从基本上表示宽频带宽信号（105）的数字化样本产生。

公开(公告)号：WO1996021280A1

公开(公告)日：1996-07-11

申请号：PCT/US1995015295

申请日：1995-11-22

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  SMITH, Paul, Fielding ,  PINCKLEY, Danny, Thomas

IPC: H03M01/12

CPC classification number: H04B1/0017 ,  H03M1/121 ,  H04B1/0003 ,  H04B1/001 ,  H04B1/26 ,  H04L1/06 ,  H04L1/22 ,  H04L25/14 ,  H04L27/2647

Abstract: A split frequency band signal digitizer (10) includes a first mixer (18) for translating a split-band signal (200) about a multiple of the sampling frequency. The split-band signal so translated is then communicated to an analog-to-digital converter (26). The digitized signal is then analyzed to recover an original portion of the split-band signal and a second portion of the signal aliased into a single Nyquist band.

Abstract translation: 分离频带信号数字转换器（10）包括一个第一混频器（18），用于将分频带信号（200）转换成采样频率的倍数。 然后将如此转换的分裂带信号传送到模数转换器（26）。 然后分析数字化信号以恢复分裂带信号的原始部分，并将信号的第二部分混叠成单个奈奎斯特频带。

公开(公告)号：WO1994028631A1

公开(公告)日：1994-12-08

申请号：PCT/US1994006046

申请日：1994-05-27

Applicant: SENSAR CORPORATION

Inventor： SENSAR CORPORATION ,  HAAB, Dan ,  PATTEN, Dan ,  ROLLINS, Richard ,  JOHNSON, Kent ,  LEE, Edgar, D.

IPC: H03M01/12

CPC classification number: G01D1/02 ,  G01D9/00

Abstract: A high speed data acquisition system which acquires an analog signal (102), converts it to digital data (104), and compresses the large volume of accumulated data into a format that can be handled in a microcomputer environment. The data acquisition system of the present invention can rapidly and continuously acquire and process large volumes of data. Included is an averaging circuit (106) which allows the present invention to efficiently process and store large amounts of data uninterruptedly. The present invention is thus well suited for applications that require uninterrupted high-speed sampling over long periods of time.

Abstract translation: 一种获取模拟信号（102）的高速数据采集系统将其转换为数字数据（104），并将大量的累积数据压缩成可在微机环境中处理的格式。 本发明的数据采集系统可以快速，连续地获取和处理大量的数据。 包括平均电路（106），其允许本发明不间断地有效地处理和存储大量的数据。 因此，本发明非常适合需要长时间不间断的高速采样的应用。

公开(公告)号：WO1992010033A1

公开(公告)日：1992-06-11

申请号：PCT/US1991009035

申请日：1991-12-03

Applicant: MORIYASU, Hiro

IPC: H03M01/12

CPC classification number: G01R13/24

Abstract: A signal acquisition system using an ultrawide time range digitizer with variable time interval data sampling and data storage includes signal conditioning and sampling stages (21), a digitizing stage (44) for generating digital representations of a signal, and a memory (23) for storing the digital representations. Timing circuitry (33, 34) controls sampling and digitizing which may be varied so as to acquire signals on linear, logarithmic, or other time bases. Signal compression may be obtained by digitizing information only when a desired change rate is observed. A display (2) allows acquired signals to be displayed in linear, logarithmic or other memory.

公开(公告)号：WO1996012349A1

公开(公告)日：1996-04-25

申请号：PCT/US1995012856

申请日：1995-10-13

Applicant: TECHNOCONCEPTS, INC.

Inventor： TECHNOCONCEPTS, INC. ,  HICKLING, Ronald, M.

IPC: H03M01/12

CPC classification number: H03M1/0682 ,  H03K5/2481 ,  H03M1/365

Abstract: A differential comparator circuit for an Analog-to-digital Converter (ADC) or other application includes a plurality of differential comparators (16) and a plurality of offset voltage generators. Each comparator includes first (T1, T2) and second (T3, T4) differentially connected transistor pairs having equal and opposite voltage offsets. First (T5) and second (T6) offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage.

Abstract translation: 用于模数转换器（ADC）或其他应用的差分比较器电路包括多个差分比较器（16）和多个偏移电压发生器。 每个比较器包括具有相等和相反电压偏移的第一（T1，T2）和第二（T3，T4）差分连接的晶体管对。 第一（T5）和第二（T6）偏移控制晶体管分别与晶体管对串联。 偏移电压发生器产生与参考电压相对应的偏移电压，该参考电压与比较器的差分输入电压进行比较。 每个偏移电压被施加到至少一个比较器的偏移控制晶体管，以将比较器的总体电压偏移设置为对应于各个参考电压的值。

公开(公告)号：WO1995008220A1

公开(公告)日：1995-03-23

申请号：PCT/US1994010268

申请日：1994-09-13

Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  CELLINI, Ronald, A. ,  SOBOL, James, M.

Inventor： ANALOG DEVICES, INC.

IPC: H03M01/12

CPC classification number: H03H17/06 ,  H03H17/0614 ,  H03H17/0628 ,  H03L7/08 ,  H03L7/093 ,  H03L7/0992 ,  H03L2207/50 ,  H03M3/498

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator. Data thus emerges from the interpolation/decimation process at the sample rate selected by the n-th order m-bit sigma-delta modulator. The method and apparatus converts the data rate of an incoming digital data stream from an ADC to the data rate determined by the n-th order m-bit sigma-delta modulator.

Abstract translation: 一种使用数字样本之间的时间间隔的Σ-Δ调制进行模数转换的方法和装置。 本发明的方法和装置提供了时基的Σ-Δ调制，使得由非均匀采样产生的误差是频率形状的区域（即，转移到更高的频率），其中它们可以通过常规滤波技术去除。 在一个实施例中，在Σ-Δ调制频率选择信号的控制下内插数字数据，该Δ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率，然后以固定比率被抽取。 在另一个实施例中，数字数据以固定比例内插，然后在Σ-Δ调制频率选择信号的控制下被抽取，该Σ-Δ调制频率选择信号平均表示要由转换器输出的数字数据的数据速率。 使用第n级m位Σ-Δ调制器调制频率选择信号。 数据因此从由第n级m比特Σ-Δ调制器选择的采样率的内插/抽取处理中出现。 该方法和装置将来自ADC的输入数字数据流的数据速率转换为由第n位m位Σ-Δ调制器确定的数据速率。

公开(公告)号：WO1993015556A1

公开(公告)日：1993-08-05

申请号：PCT/SE1993000065

申请日：1993-01-29

Applicant: SILICON CONSTRUCTION SWEDEN AB ,  SVENSSON, Christer, Martinus ,  YUAN, Jiren

Inventor： SILICON CONSTRUCTION SWEDEN AB

IPC: H03M01/12

CPC classification number: H03M1/1215 ,  H03M1/46

Abstract: The invention relates to an analog-to-digital arrangement for A/D converting a high-frequency analog input signal into a series of digital signals on-line with high sampling rate. It includes several computing channels for providing a digital signal from an analog input, each including a sample-and-hold means, to which the analog input signal is connected, a multiplexing means (3) having several inputs, each input being connected to an individual computing channel output, and, a timing circuit (4) controlling cyclically in a clock signal rate and in a prescribed order one at the time of the sample-and-hold means to hold the current analog value of the analog input signal and also to control the multiplexing means (3) to place on its output one at the time of the digital outputs of the several computing channels. All the computing channels compute the digital value of the analog value held in its sample-and-hold means during a digitizing phase simultaneously but skewed in relation to the other computing channels. Each computing channel (1.1 to 1.k+n; SA-ADC) includes a sample-and-hold means (5), to which the analog input signal is connected and at least one successive approximating analog-to-digital converter (SA-ADC). A common reference voltage generator (2) is provided having a multiline output having a different reference voltage on each line of the multiline output. All the computing channels have at least one multiline input connected in common to the multiline output of the voltage generator.

Abstract translation: 本发明涉及一种用于将高频模拟输入信号以高采样率在线地转换为一系列数字信号的A / D模数转换装置。 它包括几个用于从模拟输入提供数字信号的计算通道，每个数字信号包括连接有模拟输入信号的采样保持装置，具有多个输入的多路复用装置（3），每个输入端连接到 个别计算通道输出，以及定时电路（4），其在采样保持装置时以时钟信号速率和规定顺序周期性地进行控制，以保持模拟输入信号的当前模拟值，并且还 以在多个计算通道的数字输出时控制复用装置（3）放置在其输出端上。 所有计算通道在数字化阶段期间同时计算保持在采样保持装置中的模拟值的数字值，而与其它计算通道相反则倾斜。 每个计算通道（1.1至1.k + n; SA-ADC）包括采样保持装置（5），模拟输入信号连接到该采样和保持装置（5），以及至少一个逐次逼近模数转换器 -ADC）。 提供公共参考电压发生器（2），其具有在多线输出的每条线上具有不同参考电压的多线输出。 所有计算通道具有与电压发生器的多行输出共同连接的至少一个多行输入。

公开(公告)号：WO1997042712A1

公开(公告)日：1997-11-13

申请号：PCT/SE1997000724

申请日：1997-04-29

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (publ)

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON (publ) ,  TAN, Nianxiong

IPC: H03M01/12

CPC classification number: H03M1/168

Abstract: To convert an analog current to a digital signal using a high-speed pipelined analog-to-digital (A/D) converter, the A/D converter may comprise a current sample- and hold (S/H) circuit at the input and several identical pipelined stages, where each stage contains a current S/H circuit, a current interstage low-resolution A/D converter and current references. To improve the speed of pipelined current-mode A/D converters the capacitive load seen by the output of every stage will be reduced. By adjusting the reference currents the power consumption will also be reduced. It is possible to achieve about 100 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs. To increase the operation speed and to provide means to reduce the power consumption the pipelined current-mode A/D converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.

Abstract translation: 要使用高速流水线模数（A / D）转换器将模拟电流转换为数字信号，A / D转换器可以包括输入端的电流采样保持（S / H）电路， 几个相同的流水线阶段，其中每个阶段包含电流S / H电路，当前级间低分辨率A / D转换器和电流参考。 为了提高流水线电流模式A / D转换器的速度，每级输出所看到的容性负载将会降低。 通过调整参考电流，功耗也将降低。 与现有设计相比，可以实现大约100 Msamples / s的转换速率和降低功耗。 为了提高操作速度并提供降低功耗的手段，流水线电流模式A / D转换器可以包括作为输入的S / H电路（7）和N个流水线级（8），每个流水线级（8）包含内部 低分辨率A / D转换器（9），D / A转换器（10），S / H电路（11），参考电流源（12）和加法器/减法器（13）。 本发明架构最显着的特征是：1）内部A / D转换器和级间S / H电路的输入时间间隔; 和2）每个阶段到D / A转换器的参考电流可以不同。