公开(公告)号：WO2015062535A1

公开(公告)日：2015-05-07

申请号：PCT/CN2014/089984

申请日：2014-10-31

Applicant: METTLER TOLEDO (CHANGZHOU) PRECISION INSTRUMENT LTD. ,  METTLER TOLEDO (CHANGZHOU) MEASUREMENT TECHNOLOGY LTD. ,  METTLER TOLEDO (CHANGZHOU) SCALE & SYSTEM LTD.

Inventor： DAI, Feng ,  REBER, Daniel ,  EMERY, Jean-Christophe

IPC: G01G3/18

CPC classification number: G01G3/18 ,  G01G3/1402 ,  G01G3/1414 ,  G01L1/2268 ,  G01L1/2281 ,  G01L9/0002 ,  G01L19/0092 ,  G06J1/00

Abstract: An analog sensor (100, 500, 600, 700, 800, 900) with digital compensation function comprises: a deformation part (102) generating a deformation according to a pressure sensed by the analog sensor (100, 500, 600, 700, 800, 900), a strain gauge (104) connected to the deformation part (102) and generating a change in the resistance according to the deformation, a strain gauge bridge (106) connected to the strain gauge (104) and transferring the change in the resistance of the at least one strain gauge (104) to output a first analog signal, an analog-to-digital conversion module (108, 508, 708, 808, 908) connected to an output of the strain gauge bridge (106), receiving the first analog signal from the strain gauge bridge (106) and converting the first analog signal to a first digital signal, where the first analog signal is an analog signal representative of weight, an analog output port (116) for outputting a second analog signal, and a signal processing and output circuit (110, 510, 610, 710, 810, 910) connected between the output of the analog-to-digital conversion module (108) and the analog output port(116), compensating and converting the first digital signal into the second analog signal. The analog sensor (100, 500, 600, 700, 800, 900) may achieve high-accuracy compensation while keeping the interfaces of the analog weighing sensor to be simple.

Abstract translation: 具有数字补偿功能的模拟传感器（100,500,600,700,800,900）包括：变形部分（102），其根据由模拟传感器（100,500,600,700,800）感测的压力产生变形 ，900），连接到变形部分（102）并根据变形产生电阻变化的应变计（104），连接到应变仪（104）的应变仪桥（106） 所述至少一个应变计（104）的电阻输出第一模拟信号，连接到所述应变仪桥（106）的输出的模数转换模块（108,508,708,808,908） ，接收来自应变计电桥（106）的第一模拟信号，并将第一模拟信号转换成第一数字信号，其中第一模拟信号是代表权重的模拟信号;模拟输出端口（116），用于输出第二模拟信号 模拟信号，以及信号处理和输出电路（110,510,610 ，710，810，910），连接在模数转换模块（108）的输出端和模拟输出端口（116）之间，补偿并将第一数字信号转换为第二模拟信号。 模拟传感器（100,500,600,700,800,900）可以实现高精度补偿，同时保持模拟称重传感器的接口简单。

公开(公告)号：WO2010053780A1

公开(公告)日：2010-05-14

申请号：PCT/US2009/062338

申请日：2009-10-28

Applicant: RAYTHEON COMPANY ,  VAMPOLA, John L. ,  VEEDER, Kenton T.

Inventor： VAMPOLA, John L. ,  VEEDER, Kenton T.

IPC: G06J1/00

CPC classification number: G06J1/00

Abstract: In one or more embodiments, an apparatus and method for processing an analog signal into a digital signal includes a quantizer that converts the analog signal, which can have any value within a given range of values, into a fixed set of discrete values. An analog residue, i.e. the quantization error caused by the difference between the analog value of the integrated analog signal and the closest corresponding discrete quantized value, is outputted. The analog residue can be further processed to increase the accuracy of the A/D conversion. Multiple quantizer stages can be provided to perform A/D conversion of the analog signal over multiple integration periods, e.g. in multi-shot and time-delay integration applications. The analog signal may represent an image signal.

Abstract translation: 在一个或多个实施例中，用于将模拟信号处理为数字信号的装置和方法包括量化器，其将可以具有给定值范围内的任何值的模拟信号转换成固定的一组离散值。 输出模拟残差，即由积分模拟信号的模拟值与最接近的对应离散量化值之间的差引起的量化误差。 可以进一步处理模拟残基以提高A / D转换的精度。 可以提供多个量化器级以在多个积分周期上执行模拟信号的A / D转换，例如， 在多播和延时集成应用中。 模拟信号可以表示图像信号。

公开(公告)号：WO2006045789A1

公开(公告)日：2006-05-04

申请号：PCT/EP2005/055517

申请日：2005-10-25

Applicant: ROBERT BOSCH GMBH ,  MUELLER, Bernd ,  BOEHL, Eberhard

Inventor： MUELLER, Bernd ,  BOEHL, Eberhard

IPC: G06F11/16

CPC classification number: G06F11/1641 ,  G06F9/30021 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3869 ,  G06F9/3885 ,  G06F11/183 ,  G06F2201/845 ,  G06J1/00

Abstract: Verfahren und Vorrichtung zur Umschaltung und zum Signalvergleich bei einem Rechnersystem mit wenigstens zwei Verarbeitungseinheiten, wobei Umschaltmittel vorgesehen sind und zwischen wenigstens zwei Betriebsmodi umgeschaltet wird, wobei Vergleichsmittel vorgesehen sind und ein erster Betriebsmodus einem Vergleichsmodus und ein zweiter Betriebsmodus einem Performanzmodus entspricht, dadurch gekennzeichnet, dass wenigstens zwei analoge Signale der Verarbeitungseinheiten verglichen werden, indem wenigstens ein analoges Signal in wenigstens einen digitalen Wert gewandelt wird.

Abstract translation: 用于切换和用于在具有至少两个处理单元，其特征在于，开关装置被提供，并且被操作的至少两种模式之间切换的计算机系统中的信号相比较的方法和装置，所述设置比较装置，以及在第一操作模式到一个比较模式和第二操作模式对应于性能模式，其特征在于 的处理单元中的至少两个模拟信号由模拟信号相比的数字值是在至少转化至少。

公开(公告)号：WO2004084273A3

公开(公告)日：2005-03-24

申请号：PCT/US2004007958

申请日：2004-03-16

Applicant: INNOVEL INC

Inventor： NAZARIAN HAGOP A

IPC: G06J1/00 ,  H01L20060101 ,  H01L29/00 ,  H01L47/00 ,  H03M1/36

CPC classification number: H03K19/017581 ,  G06J1/00

Abstract: An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

Abstract translation: 混合模式集成电路系统的模拟部分包括多个模拟输入单元，多个模拟输出单元和互连阵列。 输入单元配置为编程模拟功能。 输出单元被配置为提供与编程的模拟功能相对应的模拟和数字输出。 互连阵列将编程的模拟功能处理成指示模拟功能的信号。 互连阵列选择性地将信号提供给多个模拟输出单元。

公开(公告)号：WO1998004926A1

公开(公告)日：1998-02-05

申请号：PCT/DE1997001597

申请日：1997-07-29

Applicant: D-TECH GMBH ANTRIEBSTECHNIK UND MIKROELEKTRONIK ,  NICOLAEVICH, Krosnov Mikhail ,  MICHAJLOVICH, Kouzioukine Alexej

Inventor： D-TECH GMBH ANTRIEBSTECHNIK UND MIKROELEKTRONIK

IPC: G01R21/133

CPC classification number: G01R21/133 ,  G01R22/00 ,  G06J1/00 ,  H03F2200/261

Abstract: Power measurement equipment is used to calculate the momentary value of the power actually taken from a network in which both current and voltage are variable, the voltage to a lesser but perceptible extent, the current in a distinct manner, as its effective value substantially determines the power, i.e. if current of a certain intensity is taken from the network, power has been taken, whereas if the current is practically zero, no power has been taken from the network. A multiplier circuit is disclosed for power or energy measurement equipment (P, W, 30, 40). A first measured (9) analogue signal (u) is supplied to a first sigma-delta converter (SDM1;10) whose output controls a multiplier (20; 20a, 20b, 20c, 20d; 21a, 21b, 22a, 22b). A second measured (19) analogue signal (i) is supplied to the multiplier (20). The output of the multiplier (20) is supplied to a second sigma-delta converter (SDM2; 30) which generates at its output an output signal (p(t)) which represents the momentary value of the product of the first analogue signal by the second analogue signal (u, i), hence the power to be measured.

Abstract translation: 本发明涉及的功率计，利用该电流值用于从主电源所取的电流，并且电流和网络的电压，两者都是可变的，在电压不足，但明显的，显著的电流来计算，因为他的他RMS 实质上决定的性能，特别是如果电流被采取在一定的高度（提取的功率是可用的）或功率几乎为零（没有功率被移除）。 本发明提出了一种用于动力或能量测量装置（P，W，30，40）在前面，其中，第一测量（9）模拟信号（U）的第一Σ-Δ转换器（SDM1; 10）一个乘法电路被馈送 ，乘法器装置的输出（20; 20A，20B，20C，20D; 21A，21B，22A，22B）的控制。 乘法器装置（20）被送入测量第二（19）的模拟信号（I）。 乘法器装置的输出（20）是第二Σ-Δ转换器（SDM2; 30）供给的，在其输出端的输出信号（P（t））的设置，即第一和第二模拟信号的乘积的瞬时值 （U，i）表示，因此，要测量的功率。

公开(公告)号：WO1996018243A1

公开(公告)日：1996-06-13

申请号：PCT/US1995013867

申请日：1995-10-27

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  CONNELL, Lawrence, Edwin ,  KANG, David, Dukho ,  HOLLENBECK, Neal, Wayne ,  ROECKNER, William, J.

IPC: H04B01/10

CPC classification number: H04L7/0054 ,  G06J1/00 ,  H03M1/1009 ,  H04L7/033 ,  H04L7/0334

Abstract: An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

Abstract translation: 干扰相关自适应相位时钟控制器方法和系统包括信号处理时钟信号的合成（307）。 测量依赖于信号处理时钟信号的相位的干扰信号（311），并依赖于相位校正信号（317）。 通过根据相位校正信号（317）调整信号处理时钟信号（307）的相位来减小干扰信号的大小。

公开(公告)号：WO1995001006A1

公开(公告)日：1995-01-05

申请号：PCT/US1994005419

申请日：1994-05-16

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  TRAYLOR, Kevin, Bruce

IPC: H03M01/66

CPC classification number: G06J1/00 ,  H03D7/00 ,  H03D7/165 ,  H03D2200/005 ,  H03D2200/0052 ,  H03D2200/0068 ,  H03D2200/007 ,  H03D2200/0072

Abstract: A digital-to-analog (D/A) convertor (206) multiplies an input signal by a sinewave approximation (300) to perform frequency translation. Optimized coefficient values are predetermined and are programmed based on a control word generated during a clock cycle. The programming over a time period representative of the frequency of the sinewave approximation (300) provides a signal that multiplies an input signal such that the effects of odd harmonics at an output are mitigated while the advantages of a traditional switching mixer are retained. In one embodiment the multiplying D/A convertor (206) includes a plurality of resistors (R1-R8) connected to an amplifier (400), with plural switching gates (G1-G8) switching select resistors (R1-R8) in and out of operation, a control word from counter/controller (203) controlling the gates (G1-G8).

Abstract translation: 数模（D / A）转换器（206）将输入信号乘以正弦波近似（300）进行频率转换。 优化的系数值是预定的，并且基于在时钟周期期间产生的控制字来编程。 在代表正弦波近似（300）的频率的时间段上的编程提供了将输入信号相乘的信号，使得输出端的奇次谐波的效果得到缓解，同时传统的开关混频器的优点得以保留。 在一个实施例中，乘法D / A转换器（206）包括连接到放大器（400）的多个电阻器（R1-R8），多个开关门（G1-G8）切换选择电阻器（R1-R8） 来自控制门（G1-G8）的计数器/控制器（203）的控制字。

公开(公告)号：WO1992014218A1

公开(公告)日：1992-08-20

申请号：PCT/GB1992000203

申请日：1992-02-04

Applicant: CAMBRIDGE CONSULTANTS LIMITED ,  RICHARDS, Matthew, John ,  COLLIER, James, Digby, Yarlet

Inventor： CAMBRIDGE CONSULTANTS LIMITED

IPC: G06J01/00

CPC classification number: H03B28/00 ,  G06J1/00

Abstract: A frequency synthesiser for generating a sinusoidal analogue signal comprises a digital signal generator for generating a substantially triangular digital signal. A digital to analogue converter (DAC) receives the digital signal. The DAC has a non-linear transfer function shaped to generate a sinusoidal analogue signal.

Abstract translation: 用于产生正弦模拟信号的频率合成器包括用于产生大致三角形数字信号的数字信号发生器。 数模转换器（DAC）接收数字信号。 DAC具有形状为产生正弦模拟信号的非线性传递函数。

公开(公告)号：WO1989006009A1

公开(公告)日：1989-06-29

申请号：PCT/US1988004407

申请日：1988-12-08

Applicant: QUALCOMM, INC.

Inventor： QUALCOMM, INC. ,  KERR, Richard, J. ,  WEAVER, Lindsay, A.

IPC: G06F07/38

CPC classification number: G06J1/00 ,  G06F1/0328 ,  G06F2101/04 ,  G06F2211/902

Abstract: A method and apparatus for reducing spurious output noise in digital frequency synthesizers that employ a sine amplitude converter (16) connected to a Digital-to-Analog converter (18) for generating an analog waveform from sine amplitude data. The method comprises the steps of adding random or pseudorandom numbers which are scaled to have a predetermined magnitude to the sine amplitude data and transferring a resulting addend to the Digital-to-Analog converter (18). The apparatus comprises a summation circuit (22) connected between an output of the sine function converter (18) and an input of the digital-to-analog converter and connected to a random or pseudorandom number generator (24) at a second input. A scale element (26) adjusts the pseudorandom number magnitude to provide numbers having values in the range +/- 1/2 times a minimum quantization step or at least significant bit of the Digital-to-Analog converter (18) resolution where n is greater than or equal to 1.

公开(公告)号：WO1988010474A1

公开(公告)日：1988-12-29

申请号：PCT/US1988002110

申请日：1988-06-17

Applicant: UNIVERSITY OF WEST VIRGINIA

Inventor： UNIVERSITY OF WEST VIRGINIA ,  BROWN, Paul, B.

IPC: G06G07/12

CPC classification number: G06K9/605 ,  G06J1/00 ,  G06N3/04 ,  G06N3/0635

Abstract: A neural network is implemented by discrete-time, continuous voltage state analog devices in which neuron signals (9), synapse signals (7) and synaptic strength signals (15) are generated in highly parallel analog circuits in successive states from stored values of the interdependent signals calculated in a previous state. The neuron and synapse signals are refined in a relaxation loop (9), (5), (7) while the synaptic strength signals are held constant. In learning modes, the synaptic strength signals are modified in successive states from stable values of the analog neuron signals. The analog signals are stored for as long as required in master/slave sample and hold circuits (69) as digitized signals which are periodically refreshed to maintain the stored voltage within a voltage window bracketing the original analog signal.