公开(公告)号：WO2022006006A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/039435

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LESLIE, Matthew B. ,  GREEFF, Roy E. ,  HOLLIS, Timothy M.

IPC: H04L25/03 ,  H04L25/08 ,  H04L25/02 ,  G11C7/1048 ,  G11C7/1063 ,  H04L25/03076 ,  H04L25/03146 ,  H04L25/03878

Abstract: Embodiments of the disclosure include signal processing methods to reduce crosstalk between signal lines of a channel bus using feed forward equalizers (FFEs) configured smear pulse response energy transmitted on signal lines of the channel to reduce pulse edge rates. The coefficients for the FFE may be based on crosstalk interference characteristics. Smearing or spreading pulse response energy across a longer time period using a FFE increases inter-symbol interference (ISI). To counter increased inter-symbol interference caused by smearing pulse response energy, receivers configured to recover symbol data transmitted on the channel bus may each include respective decision-feedback equalizers (DFEs) that are configured to filter ISI from transmitted symbols based on previous symbol decisions of the channel. The combination of the FFE configured to smear pulse responses and the DFE to filter ISI may improve data eye quality for recovery of transmitted data on a channel bus when crosstalk dominates noise.

公开(公告)号：WO2022115849A2

公开(公告)日：2022-06-02

申请号：PCT/US2021/072568

申请日：2021-11-23

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SONI, Ravish

IPC: H04L25/03 ,  H03K17/6871 ,  H03K5/133 ,  H04L2025/03445 ,  H04L25/03057 ,  H04L25/03146

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：WO2021142459A1

公开(公告)日：2021-07-15

申请号：PCT/US2021/012993

申请日：2021-01-11

Applicant: MARVELL ASIA PTE, LTD.

Inventor： WU, Xing ,  JIN, Yuansheng ,  XU, Junyi ,  LIN, Jian-Hung ,  DAI, Shaoan

IPC: H04L25/03 ,  H04L2025/0349 ,  H04L2025/03579 ,  H04L2025/03617 ,  H04L25/03031 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/03885

Abstract: Data symbols in an input signal are detected with a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated, during a particular clock cycle, based on a first set of one or more data symbols detected during first one or more previous clock cycles and a second set of one or more data symbols detected during second one or more previous clock cycles. The second set is separated from the first set by a third set of one or more data symbols detected during third one or more clock cycles that occur after the first one or more clock cycles and before the second one or more clock cycles, where the output is generated without use of the third set of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.