公开(公告)号：WO2023092047A1

公开(公告)日：2023-05-25

申请号：PCT/US2022/080095

申请日：2022-11-18

Applicant: APPLIED MATERIALS, INC.

Inventor： KANG, Chang Seok ,  KITAJIMA, Tomohiko ,  LEE, Gill Yong ,  PRANATHARTHIHARAN, Balasubramanian ,  SRINIVASAN, Mukund

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/50

Abstract: Described is a memory device including a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate. Each of the plurality of memory cells comprises a discrete blocking oxide layer, a charge trap layer, and a tunnel oxide layer. The blocking oxide layer is discrete between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trap layer is discrete between each of the plurality of memory cells. The charge trap layer has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness.

公开(公告)号：WO2023075856A2

公开(公告)日：2023-05-04

申请号：PCT/US2022/029316

申请日：2022-05-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  AMANO, Fumitaka ,  ISHIKAWA, Kensuke

IPC: H10B43/50 ,  H10B41/50 ,  H10B43/27 ,  H10B41/27 ,  H01L21/768

Abstract: A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

公开(公告)号：WO2023075544A1

公开(公告)日：2023-05-04

申请号：PCT/KR2022/016815

申请日：2022-10-31

Applicant: 한양대학교 산학협력단

Inventor： 송윤흡 ,  심재민

IPC: H10B43/35 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50 ,  H10B43/30

Abstract: 집적화를 개선하고, 적층 구조체 내 하나의 넓은 면적으로 형성되는 워드 라인으로 인한 프린징 필드의 영향성을 개선하는 3차원 플래시 메모리 및 그 제조 방법이 개시된다. 상기 3차원 플래시 메모리는 수평 방향으로 연장 형성되며 수직 방향으로 교대로 적층된 층간 절연막들 및 워드 라인들, 상기 층간 절연막들 및 상기 워드 라인들을 상기 수직 방향으로 관통하며 연장 형성되는 수직 채널 구조체들, 및 수직 채널 구조체들을 수평 평면 상에서 서로 연결시키며 상기 수직 방향으로 연장 형성되는 적어도 하나의 수직 연결 패턴을 포함한다.

公开(公告)号：WO2023049132A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/044165

申请日：2022-09-21

Applicant: MONOLITHIC 3D INC.

Inventor： OR-BACH, Zvi ,  HAN, Jin-Woo ,  CRONQUIST, Brian

IPC: H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H01L23/528 ,  H01L23/367 ,  H04L25/02 ,  H04L27/26 ,  G06N3/08

Abstract: A semiconductor device, the device including: a first level including a plurality of first transistors, where at least one of the plurality of first transistors includes a single crystal channel; a first interconnect layer disposed on top of the plurality of first transistors; a plurality of ground lines disposed underneath the plurality of first transistors, the plurality of ground lines connecting from a ground to at least one of the plurality of first transistors; a plurality of power lines disposed underneath the plurality of first transistors, the plurality of power lines connecting from power to at least one of the plurality of first transistors; and a heat conductive material disposed so to be in contact with the plurality of ground lines and the plurality of power lines, where the heat conductive material includes diamond molecules.