公开(公告)号：WO2023083699A1

公开(公告)日：2023-05-19

申请号：PCT/EP2022/080746

申请日：2022-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： XIE, Ruilong ,  LOUBET, Nicolas ,  FROUGIER, Julien ,  CLEVENGER, Lawrence ,  BHOSALE, Prasad ,  WANG, Junli ,  PRANATHARTHIHARAN, Balasubramanian ,  GUO, Dechao

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/06 ,  H01L29/775

Abstract: Vertically stacked field-effect transistors (FETs) with independent and shared gates are disclosed. The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

公开(公告)号：WO2023078652A1

公开(公告)日：2023-05-11

申请号：PCT/EP2022/078469

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： FROUGIER, Julien ,  LOUBET, Nicolas ,  GREENE, Andrew ,  XIE, Ruilong ,  BHUIYAN, Maruf Amin ,  BASKER, Veeraraghavan

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.

公开(公告)号：WO2023066793A1

公开(公告)日：2023-04-27

申请号：PCT/EP2022/078602

申请日：2022-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： XIE, Ruilong ,  FAN, Su Chen ,  BASKER, Veeraraghavan ,  FROUGIER, Julien ,  LOUBET, Nicolas

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/775

Abstract: A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material (cut Y4), a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate (cut Yl), the metal link disposed above the second dielectric material, a first source/drain (S/D) contact (810, cut Y3) disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact (810, cut Y2) disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

公开(公告)号：WO2023000471A1

公开(公告)日：2023-01-26

申请号：PCT/CN2021/117419

申请日：2021-09-09

Applicant: 长鑫存储技术有限公司

Inventor： 赵文礼 ,  白杰

IPC: H01L21/8238

Abstract: 本公开涉及半导体技术领域，提出了一种半导体结构及半导体结构的制作方法。半导体结构包括衬底、NMOS晶体管以及PMOS晶体管，NMOS晶体管包括依次叠置的第一电介质层、第一功函数层以及第一导电层，PMOS晶体管包括依次叠置的第二电介质层、第二功函数层以及第二导电层。在半导体结构的制作过程中，会导致第一功函数层和第二功函数层内的金属元素扩散，可能会影响半导体结构阈值电压的调节，通过在第一功函数层朝向第二功函数层的一侧设置有第一侧壁隔离层，和/或，第二功函数层朝向第一功函数层的一侧设置有第二侧壁隔离层，可以阻止金属元素的交叉扩散，以此避免半导体结构阈值电压难以被调节的情况，从而改善半导体结构的性能。

公开(公告)号：WO2022260478A1

公开(公告)日：2022-12-15

申请号：PCT/KR2022/008227

申请日：2022-06-10

Applicant: 주성엔지니어링(주)

Inventor： 황철주

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/02

Abstract: 본 발명의 실시예에 따른 활성층 형성 단계는, 제1영역과 제2영역을 포함하는 SiC 기판을 준비하는 단계, SiC 기판의 제1영역으로 제1도핑가스와 혼합된 소스가스, 퍼지가스, 리액턴트 가스, 퍼지가스를 순차적으로 분사하여 제1활성층을 형성하는 단계 및 SiC 기판의 제2영역으로 제2도핑가스와 혼합된 소스가스, 퍼지가스, 리액턴트 가스, 퍼지가스를 순차적으로 분사하여 제2활성층을 형성하는 단계를 포함한다. 따라서, 본 발명의 실시예들에 의하면, 저온에서 활성층을 형성할 수 있다. 따라서 기판 또는 그 상부에 형성된 박막이 고온의 열에 의해 손상되는 것을 방지할 수 있다. 또한, 활성층 형성을 위해 기판을 승온시키는 전력 또는 시간을 절약할 수 있고, 전체 공정 시간을 단축시킬 수 있다.

公开(公告)号：WO2022258151A1

公开(公告)日：2022-12-15

申请号：PCT/EP2021/065305

申请日：2021-06-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BHUWALKA, Krishna, Kumar

Inventor： BHUWALKA, Krishna, Kumar

IPC: H01L29/775 ,  H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  B82Y10/00

Abstract: A semiconductor architecture includes a substrate, an n-type transistor, and a p-type transistor, each formed on the substrate. Each of the n-type transistor and the p-type transistor of the semiconductor architecture includes a plurality of finger sub-devices, and each finger sub-device includes a plurality of stacked semiconductors. One or more of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a forkstack device including a dielectric barrier that extends down one side only of the stacked semiconductors. The semiconductor architecture along with the multi-finger architecture is beneficial for high-current devices and power-performance trade-off devices.

公开(公告)号：WO2022243135A1

公开(公告)日：2022-11-24

申请号：PCT/EP2022/062803

申请日：2022-05-11

Applicant: INFINEON TECHNOLOGIES AUSTRIA AG

Inventor： MEISER, Andreas Peter ,  SCHLOESSER, Till ,  HENSON, Timothy

IPC: H01L21/8234 ,  H01L21/765 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/78 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: The disclosure relates to a semiconductor die (1), comprising a vertical power transistor device (2), the vertical power transistor device having a source region (3) and a drain region (4) at opposite sides of a semiconductor body (10), and a lateral transistor device (20), the lateral transistor device having a body region (221) with a lateral channel region (221.1), as well as a source and a drain region formed at a frontside of the semiconductor body, wherein a deep trench (305) is arranged laterally between the vertical power transistor device (2) and the lateral transistor device (20), forming a deep trench isolation (306).

公开(公告)号：WO2022240733A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028301

申请日：2022-05-09

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： CHANEMOUGAME, Daniel ,  LIEBMANN, Lars ,  SMITH, Jeffrey ,  GUTWIN, Paul

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

公开(公告)号：WO2022147984A1

公开(公告)日：2022-07-14

申请号：PCT/CN2021/103732

申请日：2021-06-30

Applicant: 长鑫存储技术有限公司

Inventor： 杨蒙蒙 ,  白杰

IPC: H01L21/8238

Abstract: 本申请实施例属于半导体制作技术领域，涉及一种半导体结构制作方法及半导体结构，用于解决半导体结构性能较差的问题。该半导体结构制作方法包括：提供基底，基底包括第一区域以及第二区域；在基底上形成介质层；在介质层上形成具有第一金属氧化物层的第一扩散膜层；去除第二区域对应的第一扩散膜层；在第二区域对应的介质层上形成第二扩散膜层，第二扩散膜层包括与介质层接合的第二金属氧化物层；退火处理，使第一金属氧化物层中的第一金属元素扩散至第一区域对应的介质层中，同时使第二金属氧化物层中的第二金属元素扩散至第二区域对应的介质层中；由于第二金属氧化物层与介质层接触，第二金属元素易扩散至介质层中，从而提高半导体的性能。

公开(公告)号：WO2022130451A1

公开(公告)日：2022-06-23

申请号：PCT/JP2020/046526

申请日：2020-12-14

Applicant: ユニサンティス　エレクトロニクス　シンガポール　プライベート　リミテッド ,  金澤　賢一

Inventor： 金澤　賢一 KANAZAWA Kenichi

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

Abstract: 半導体柱を囲むゲート導体層の形成方法において、耐酸化性をもつ第２及び第１のマスク材料層を各々半導体柱頂部と半導体柱側壁に形成し、全体に、熱的又は化学的に酸化を施し、露出した第１の不純物領域表面に第１の絶縁層を形成し、次に前記第１のマスク材料層を除去し、前記第１の絶縁層上部にゲート導体層を形成する。