公开(公告)号：WO2022207660A1

公开(公告)日：2022-10-06

申请号：PCT/EP2022/058312

申请日：2022-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

Inventor： REZNICEK, Alexander ,  XIE, Ruilong ,  HEKMATSSHOATABARI, Bahman ,  NING, Tak

IPC: H01L29/775 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  B82Y10/00 ,  H01L2029/7858 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.

公开(公告)号：WO2021247167A1

公开(公告)日：2021-12-09

申请号：PCT/US2021/029595

申请日：2021-04-28

Applicant: QUALCOMM INCORPORATED

Inventor： YUAN, Jun ,  FENG, Peijie ,  SONG, Stanley Seungchul ,  RIM, Kern

IPC: B82Y10/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/423 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: Gate-all-around (GAA) transistors (200) with an additional bottom channel (234) for reduced parasitic capacitance and methods of fabricating the same include one or more channels (210) positioned between a source region (230) and a drain region (232). The one or more channels, which may be nanowire or nanoslab semiconductors are surrounded by gate material (212). The GAA transistor further includes an additional semiconductor channel (234) between a bottom section of a gate material and a silicon on insulator (SOI) substrate (218, 220) in a GAA transistor. This additional channel, sometimes referred to as a bottom channel, may be thinner than other channels in the GAA transistor and may have a thickness less than its length.

公开(公告)号：WO2022269447A1

公开(公告)日：2022-12-29

申请号：PCT/IB2022/055686

申请日：2022-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM (CHINA) INVESTMENT COMPANY LTD. ,  IBM DEUTSCHLAND GMBH

Inventor： XIE, Ruilong ,  MILLER, Eric ,  GUO, Dechao ,  SHEARER, Jeffrey ,  FAN, Su Chen ,  FROUGIER, Julien ,  BASKER, Veeraraghavan ,  WANG, Junli ,  SUK, Sung Dae

IPC: H01L27/088 ,  H01L21/336 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02609 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

公开(公告)号：WO2022268670A1

公开(公告)日：2022-12-29

申请号：PCT/EP2022/066654

申请日：2022-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： ZHANG, Jingyun ,  XIE, Ruilong ,  VEGA, Reinaldo ,  CHENG, Kangguo ,  YU, Lan

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L21/336 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate stack (142) and an epitaxial layer (136). The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet (102). The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region (160) located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

公开(公告)号：WO2021255559A1

公开(公告)日：2021-12-23

申请号：PCT/IB2021/054687

申请日：2021-05-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： ZHAO, Kai ,  SIDDIQUI, Shahab ,  DECHENE, Daniel, James ,  KRISHNAN, Rishikesh ,  ADAMS, Charlotte DeWan

IPC: H01L21/336 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：WO2021080908A1

公开(公告)日：2021-04-29

申请号：PCT/US2020/056282

申请日：2020-10-19

Applicant: APPLIED MATERIALS, INC.

Inventor： COLOMBEAU, Benjamin ,  GOSSMANN, Hans-Joachim

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：WO2022240733A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028301

申请日：2022-05-09

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： CHANEMOUGAME, Daniel ,  LIEBMANN, Lars ,  SMITH, Jeffrey ,  GUTWIN, Paul

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

公开(公告)号：WO2022010664A1

公开(公告)日：2022-01-13

申请号：PCT/US2021/039052

申请日：2021-06-25

Applicant: APPLIED MATERIALS, INC.

Inventor： STOLFI, Michael ,  KIM, Myungsun ,  COLOMBEAU, Benjamin ,  NATARAJAN, Sanjay

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：WO2021259478A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067773

申请日：2020-06-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

Inventor： BADAROGLU, Mustafa

IPC: H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/336 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method of producing Gate-AII-Around (GAA) devices on a semiconductor wafer. The method includes defining a first area and etching the first area to obtain a first space for the first GAA device. The method further includes applying a first stack in the first space, by alternatingly applying nanosheets and spacer elements and applying a final layer of the etchable material. The method includes defining a second area and etching the second area to obtain a second space for the second GAA device. The method further includes applying a second stack in the second space, and applying a final layer of the etchable material. Notably, the first stack and the second stack differ from one another with respect to one or more of the number of nanosheets, the thickness of each nanosheet, and the height of the spacer elements.

公开(公告)号：WO2021255570A1

公开(公告)日：2021-12-23

申请号：PCT/IB2021/054905

申请日：2021-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED

Inventor： LI, Tao ,  KANG, Tsung-Sheng ,  XIE, Ruilong ,  REZNICEK, Alexander ,  GLUSCHENKOV, Oleg

IPC: H01L27/088 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor device designs having a buried power rail (602) with a sloped epitaxy buried contact (1702) are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate (202); source and drains (906) on opposite sides of the at least one gate, wherein at least one of the source and drains (906) has a sloped surface (1402); a buried power rail (602) embedded in the substrate (202); and a buried contact (1702) that connects the buried power rail (602) to the sloped surface (1402) of the at least one source and drain (906). Sidewall spacers (502) separate the buried power rail (602) from the substrate (202). A top of the sloped surface (1402) of the at least one source and drain (906) is above a top surface of the buried contact (1702).Methods of forming a semiconductor FET device are also provided.