公开(公告)号：WO2023083699A1

公开(公告)日：2023-05-19

申请号：PCT/EP2022/080746

申请日：2022-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： XIE, Ruilong ,  LOUBET, Nicolas ,  FROUGIER, Julien ,  CLEVENGER, Lawrence ,  BHOSALE, Prasad ,  WANG, Junli ,  PRANATHARTHIHARAN, Balasubramanian ,  GUO, Dechao

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/06 ,  H01L29/775

Abstract: Vertically stacked field-effect transistors (FETs) with independent and shared gates are disclosed. The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

公开(公告)号：WO2023066793A1

公开(公告)日：2023-04-27

申请号：PCT/EP2022/078602

申请日：2022-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

Inventor： XIE, Ruilong ,  FAN, Su Chen ,  BASKER, Veeraraghavan ,  FROUGIER, Julien ,  LOUBET, Nicolas

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/775

Abstract: A CMOS (complementary metal-oxide semiconductor) device includes an n-channel metal-oxide semiconductor (NMOS) device, a p-channel metal-oxide semiconductor (PMOS) device, the NMOS and the PMOS device surrounded by a first dielectric material, the NMOS device separated from the PMOS device by a second dielectric material, a first NMOS gate separated from a first PMOS gate by the second dielectric material (cut Y4), a second NMOS gate electrically connected to a second PMOS gate by a metal link disposed between the NMOS gate and the PMOS gate (cut Yl), the metal link disposed above the second dielectric material, a first source/drain (S/D) contact (810, cut Y3) disposed above the second dielectric material, the first S/D contact disposed in contact with both NMOS S/D region and a PMOS S/D region, and a second S/D contact (810, cut Y2) disposed adjacent to the second dielectric material, the second S/D contact disposed in contact with a single S/D region.

公开(公告)号：WO2023029566A1

公开(公告)日：2023-03-09

申请号：PCT/CN2022/092008

申请日：2022-05-10

Applicant: 长鑫存储技术有限公司

Inventor： 杨桂芬

IPC: H01L27/092

Abstract: 本公开涉及一种半导体结构及其制作方法。半导体结构包括第一导电类型阱区，第一导电类型阱区包括：第一器件区，第一器件区内形成有第一有源区，第一有源区形成有第一器件单元，第一器件单元用于提供第一类驱动电流；第二器件区，与第一器件区在第一导电类型阱区的长度方向上相连，第二器件区内形成有第二有源区，第二有源区形成有第二器件单元，第二器件单元用于提供第二类驱动电流，第二类驱动电流的电流值高于第一类驱动电流的电流值；第一器件区与第二器件区的阱区宽度相同。本公开能够有效提高半导体产品性能以及良率。

公开(公告)号：WO2023028856A1

公开(公告)日：2023-03-09

申请号：PCT/CN2021/115748

申请日：2021-08-31

Applicant: 长江存储科技有限责任公司

Inventor： 黄腾 ,  华子群 ,  石艳伟 ,  姚兰

IPC: H01L27/092 ,  H01L29/10

Abstract: 本发明公开了一种半导体器件的制作方法及半导体器件。所述方法包括: 在衬底中分别形成第一底部隔离层和第二底部隔离层，第二底部隔离层的厚度小于第一底部隔离层的厚度; 在衬底的第一有源区上形成延伸至第一底部隔离层的第一栅极结构，在衬底的第二有源区上形成延伸至第二底部隔离层的第二栅极结构。

公开(公告)号：WO2023010980A1

公开(公告)日：2023-02-09

申请号：PCT/CN2022/096203

申请日：2022-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM (CHINA) CO., LIMITED

Inventor： XIE, Ruilong ,  FROUGIER, Julien ,  WU, Heng ,  ZHANG, Chen ,  CHENG, Kangguo

IPC: H01L27/088 ,  H01L27/092

Abstract: A complementary metal-oxide semiconductor device formed by fabricating CMOS nanosheet stacks, forming a dielectric pillar dividing the CMOS nanosheet stacks, forming CMOS FET pairs on either side of the dielectric pillar, and forming a gate contact for at least one of the FETs.

公开(公告)号：WO2023009247A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/034440

申请日：2022-06-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MIYASHITA, Toshihiko ,  MOCUTA, Dan

IPC: H01L27/108 ,  H01L27/092 ,  H01L29/78

Abstract: DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device, The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge¬ storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one ooff the wordlines aanndd comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET. The sense-line- amplifier transistors and the wordline-driver transistors individually comprise two source/drain regions that individually comprise conductively- doped epitaxial semiconductor material that is adjacent one of two laterally- opposing sides of the at least one fin in a vertical cross-section. Methods are also disclosed.

公开(公告)号：WO2023284556A1

公开(公告)日：2023-01-19

申请号：PCT/CN2022/102649

申请日：2022-06-30

Applicant: 长鑫存储技术有限公司

Inventor： 池性洙 ,  张凤琴 ,  金书延

IPC: H01L27/108 ,  H01L27/092 ,  H01L27/02

Abstract: 本公开实施例提供一种字线驱动器、字线驱动器阵列及半导体结构，涉及半导体技术领域，所述字线驱动器包括：第零PMOS管、第零NMOS管和第一NMOS管，所述第零PMOS管的栅极与所述第一NMOS管的栅极连接，栅极用于接收第一控制信号，源极用于接收第二控制信号，漏极与所述第一NMOS管的漏极连接，所述第零NMOS管的栅极用于接收第二控制互补信号，所述第零NMOS管的漏极和所述第一NMOS管的漏极用于与字线连接；其中，所述字线具有第一延伸方向，所述第零PMOS管、所述第零NMOS管和所述第一NMOS管在所述第一延伸方向上并排设置。

公开(公告)号：WO2022258151A1

公开(公告)日：2022-12-15

申请号：PCT/EP2021/065305

申请日：2021-06-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  BHUWALKA, Krishna, Kumar

Inventor： BHUWALKA, Krishna, Kumar

IPC: H01L29/775 ,  H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  B82Y10/00

Abstract: A semiconductor architecture includes a substrate, an n-type transistor, and a p-type transistor, each formed on the substrate. Each of the n-type transistor and the p-type transistor of the semiconductor architecture includes a plurality of finger sub-devices, and each finger sub-device includes a plurality of stacked semiconductors. One or more of the finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a forkstack device including a dielectric barrier that extends down one side only of the stacked semiconductors. The semiconductor architecture along with the multi-finger architecture is beneficial for high-current devices and power-performance trade-off devices.

公开(公告)号：WO2022243135A1

公开(公告)日：2022-11-24

申请号：PCT/EP2022/062803

申请日：2022-05-11

Applicant: INFINEON TECHNOLOGIES AUSTRIA AG

Inventor： MEISER, Andreas Peter ,  SCHLOESSER, Till ,  HENSON, Timothy

IPC: H01L21/8234 ,  H01L21/765 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/78 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

Abstract: The disclosure relates to a semiconductor die (1), comprising a vertical power transistor device (2), the vertical power transistor device having a source region (3) and a drain region (4) at opposite sides of a semiconductor body (10), and a lateral transistor device (20), the lateral transistor device having a body region (221) with a lateral channel region (221.1), as well as a source and a drain region formed at a frontside of the semiconductor body, wherein a deep trench (305) is arranged laterally between the vertical power transistor device (2) and the lateral transistor device (20), forming a deep trench isolation (306).

公开(公告)号：WO2022240733A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/028301

申请日：2022-05-09

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： CHANEMOUGAME, Daniel ,  LIEBMANN, Lars ,  SMITH, Jeffrey ,  GUTWIN, Paul

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.