基準電圧回路
    1.
    发明申请
    基準電圧回路 审中-公开
    参考电压电路

    公开(公告)号:WO2013140852A1

    公开(公告)日:2013-09-26

    申请号:PCT/JP2013/051707

    申请日:2013-01-28

    CPC classification number: G05F3/24 G05F3/262 G05F3/30 H03F1/301 H03F3/345

    Abstract:  任意の出力電圧で任意の温度特性に調整することができる基準電圧回路を提供する。 複数のPN接合素子の順方向電圧の差を電流変換し第一の電流を発生する基準電流発生回路と、基準電流発生回路で発生した第一の電流を用いて第二の電流を発生させる電流発生回路と、第一の電流が流れることによって正の温度特性を有する第一の電圧を発生させる第一の抵抗素子と、第一の電流と第二の電流が流れることによって負の温度特性を有する第二の電圧を発生させる第二の抵抗素子を有する電圧発生回路を備え、第一の電圧と第二の電圧を加算した基準電圧を出力するように構成した。

    Abstract translation: 提供一种能够在任何输出电压下调节任何温度特性的参考电压电路。 本发明提供有:基准电流产生电路,用于将多个PN结装置的正向电压之间的差转换为电流并产生第一电流; 电流产生电路,用于使用由基准电流产生电路产生的第一电流产生第二电流; 以及具有第一电阻器的电压产生电路,其中第一电流的流量产生具有正温度特性的第一电压;以及第二电阻器,其中第一电流和第二电流的流量产生具有 负温度特性。 本发明被配置为使得通过添加第一电压和第二电压而获得的参考电压被输出。

    CIRCUIT THAT OPERATES IN A MANNER SUBSTANTIALLY COMPLEMENTARY TO AN AMPLIFYING DEVICE INCLUDED THEREIN AND APPARATUS INCORPORATING SAME
    3.
    发明申请
    CIRCUIT THAT OPERATES IN A MANNER SUBSTANTIALLY COMPLEMENTARY TO AN AMPLIFYING DEVICE INCLUDED THEREIN AND APPARATUS INCORPORATING SAME 审中-公开
    在包括其中的放大器件和与其同时进行的器件的大量操作中,操作的电路

    公开(公告)号:WO0139366A3

    公开(公告)日:2002-03-07

    申请号:PCT/US0041883

    申请日:2000-11-03

    Applicant: JL AUDIO INC

    CPC classification number: H03F3/345 H03F1/301

    Abstract: A circuit (200) includes a four-terminal voltage controlled voltage source (VCVS, 201) coupled to a three-terminal amplifying device (203), whereby when an input signal is applied to a negative input terminal (205) of the VCVS (201), the circuit (200) operates in a manner substantially complementary to the amplifying device (203). Such a circuit (200) may be considered a "virtual" three-terminal amplifying device and may be beneficially coupled in a complementary manner with another three-terminal amplifying device that is substantially identical to the three-terminal amplifying device (203) included in the circuit (200) to form a composite amplifier circuit that achieves intended performance over varying operating conditions.

    Abstract translation: 电路(200)包括耦合到三端放大装置(203)的四端电压控制电压源(VCVS,201),由此当输入信号施加到VCVS的负输入端(205)时 201),电路(200)以与放大装置(203)基本互补的方式操作。 这样的电路(200)可以被认为是“虚拟”三端放大装置,并且可以以与互补的方式有利地与另一个三端放大装置耦合,该三端放大装置基本上与包括在三端放大装置 电路(200)以形成在变化的工作条件下实现预期性能的复合放大器电路。

    OUTPUT BUFFER HAVING A PREDRIVER FOR COMPENSATING SLEW RATE AGAINST PROCESS VARIATIONS
    4.
    发明申请
    OUTPUT BUFFER HAVING A PREDRIVER FOR COMPENSATING SLEW RATE AGAINST PROCESS VARIATIONS 审中-公开
    具有预处理器的输出缓冲器用于补偿过程变化的更高速率

    公开(公告)号:WO99035545A1

    公开(公告)日:1999-07-15

    申请号:PCT/US1998/027445

    申请日:1998-12-21

    CPC classification number: H03K19/00384

    Abstract: An output buffer (320) incorporating a compensation circuit (370) and a predriver (310) and having compensated slew rates which are compensated against process variations is provided. The predriver (310) comprises an amplifier (250) and a transistor (240) having a gate coupled to an output of the amplifier.

    Abstract translation: 提供了包括补偿电路(370)和预驱动器(310)并且具有补偿压摆率的输出缓冲器(320),所述补偿压摆率被补偿到过程变化。 预驱动器(310)包括具有耦合到放大器的输出的栅极的放大器(250)和晶体管(240)。

    INTEGRATED CIRCUIT, CURRENT MIRROR CIRCUIT, AND METHOD OF FABRICATING CURRENT MIRROR CIRCUIT
    5.
    发明申请
    INTEGRATED CIRCUIT, CURRENT MIRROR CIRCUIT, AND METHOD OF FABRICATING CURRENT MIRROR CIRCUIT 审中-公开
    集成电路,电流反射电路以及制作电流反射电路的方法

    公开(公告)号:WO99031797A1

    公开(公告)日:1999-06-24

    申请号:PCT/JP1998/005658

    申请日:1998-12-15

    Abstract: In a integrated circuit, a mirrored current is fed to a high-impedance output node. A load is connected to the output node, and a returned current is proportional to or equal to the current supplied from a reference current source. The integrated circuit or current mirror circuit is provided with a pair of output transistors connected in series between the output node and a reference terminal. The channel of one of the output transistors is short so that the threshold voltage may be lower than that of the other transistor having a long channel. Thus, the transistors are the outcome of the high-density integrated-circuit fabrication method, and more specifically, a short-channel effect produced by a channel length of 1 mu m or less is exploited. The difference between the threshold voltages of the pair of output transistors and mutual connection between the gates of the transistors lead to minimization of the operating voltage of a current mirror circuit and maximization of the output impedance and the output swing from the output terminal of the current mirror circuit.

    Abstract translation: 在集成电路中,将镜像电流馈送到高阻抗输出节点。 负载连接到输出节点,返回的电流与从参考电流源提供的电流成比例。 集成电路或电流镜电路具有串联连接在输出节点和参考端之间的一对输出晶体管。 输出晶体管之一的沟道较短,使得阈值电压可能低于具有长沟道的另一个晶体管的阈值电压。 因此,晶体管是高密度集成电路制造方法的结果,更具体地说,利用由1微米或更小的沟道长度产生的短沟道效应。 一对输出晶体管的阈值电压之间的差异和晶体管的栅极之间的相互连接导致电流镜电路的工作电压的最小化,以及从电流的输出端子输出阻抗和输出摆幅的最大化 镜电路。

    CURRENT ONE-SHOT CIRCUIT
    6.
    发明申请
    CURRENT ONE-SHOT CIRCUIT 审中-公开
    目前的一次电路

    公开(公告)号:WO9720384A3

    公开(公告)日:1997-07-31

    申请号:PCT/IB9601261

    申请日:1996-11-20

    Inventor: MARTIN BRIAN C

    CPC classification number: H03F3/345

    Abstract: A one-shot current circuit which generates a current for a desired period, the desired period being inversely proportional to the edge rate of an input signal. The circuit includes a MOS transistor device which selectively conducts current between an input terminal and a current generating circuit. The current generating circuit can be bipolar transistor having its base coupled to the input terminal and a main current path between a circuit output and a supply voltage.

    GATE MODULATED TRANSIMPEDANCE AMPLIFIER WITH BUFFERING FOR FOCAL PLANE ARRAY
    7.
    发明申请
    GATE MODULATED TRANSIMPEDANCE AMPLIFIER WITH BUFFERING FOR FOCAL PLANE ARRAY 审中-公开
    GATE调制转移放大器与缓冲区域平面阵列

    公开(公告)号:WO8704026A1

    公开(公告)日:1987-07-02

    申请号:PCT/US8602750

    申请日:1986-12-16

    Inventor: WHITNEY COLIN G

    CPC classification number: H03K17/78 H03F1/086 H03F1/223 H03F3/082 H03F3/345

    Abstract: An improved circuit for coupling the output of a photodetector in a focal plane array to a charge coupled device. The improvement comprises amplifier means coupled between the gate of the photodetector output and an output FET for lowering the overall circuit impedance, for reducing the effect of photodetector and FET nonuniformities on the output current and for reducing the size of resistive circuit components. The amplifier may use a cascade of gate modulated FETs, at least one of which is source coupled to the photodetector output, to enhance circuit performance. The amplifiers' gain and impedance may be selectively varied by adjusting a single bias voltage.

    Abstract translation: 一种用于将焦平面阵列中的光电检测器的输出耦合到电荷耦合器件的改进的电路。 该改进包括耦合在光电检测器输出的栅极和用于降低总体电路阻抗的输出FET之间的放大器装置,用于降低光电检测器的效应和FET不均匀性对输出电流的影响并减小电阻电路部件的尺寸。 放大器可以使用级联的栅极调制FET,其中至少一个源极耦合到光电检测器输出,以增强电路性能。 可以通过调整单个偏置电压来选择性地改变放大器的增益和阻抗。

    CURRENT MIRROR PRE-BIAS FOR INCREASED TRANSITION SPEED

    公开(公告)号:WO2023018563A1

    公开(公告)日:2023-02-16

    申请号:PCT/US2022/038879

    申请日:2022-07-29

    Abstract: Methods and devices for speeding up the onset of a target current through an output leg of a current mirror are presented. Upon activation of the current mirror, a pre-charge current is sourced to a node of the current mirror that is common to the output leg and an input leg of the current mirror. Sourcing of the pre-charge current is based on sensing, by a first transistor, of a voltage at the common node. Pre-charging of the common node continues up to a cutoff voltage sensed at the common node. Sourcing of the pre-charge current is provided by a second transistor coupled to the common node. Based on the voltage sensed at the common node, the first transistor controls the sourcing of the pre-charge current by the second transistor. Such control is based on a portion of a current from a current source that flows through the first transistor.

    ELECTRET CAPSULE
    9.
    发明申请
    ELECTRET CAPSULE 审中-公开

    公开(公告)号:WO2022056610A1

    公开(公告)日:2022-03-24

    申请号:PCT/AU2021/051101

    申请日:2021-09-21

    Abstract: The present invention relates generally to the field of electret capsule, and more particularly to a circuit configuration of an impedance converter integrated in an electret capsule such as for use in condenser microphones. The electret capsule of a microphone may include a gate biasing field effect transistor (FET) to facilitate biasing of a low noise FET. Advantageously, the use of low noise FET in the electret capsule of a microphone provides for a reduced cost, while achieving lower self-noise.

    半導体装置およびセンサシステム

    公开(公告)号:WO2019239752A1

    公开(公告)日:2019-12-19

    申请号:PCT/JP2019/018640

    申请日:2019-05-09

    Abstract: ノイズ耐性の向上を実現可能な半導体装置およびセンサシステムを提供する。そこで、半導体装置内の出力回路106aは、入力端子207n,207pおよび出力端子208と、入力端子207n,207pを出力端子208に接続する出力アンプ201と、出力端子208を入力端子207nに帰還するフィードバック素子203と、スイッチ用トランジスタ204と、抵抗素子206とを有する。スイッチ用トランジスタ204のドレインは、入力端子207nに接続される。抵抗素子206は、スイッチ用トランジスタ204のバックゲートと電源Vddとの間に設けられ、入力端子207nに生じる所定の周波数のノイズを抑制するための所定の値以上のインピーダンスを備える。

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