US09544159B2
A base station receives channel state information corresponding to each of spare coordinated groups from each of user devices. A first group includes a plurality of coordinated groups arranged in advance. The spare coordinated groups corresponding to each user device are such as selected from the first group and include at least a service sector of best channel quality obtained measurement by the user device. The base station specifies a user device group corresponding to each of coordinated groups contained in each of coordinated group patterns. The user device group corresponding to the coordinated group is formed of user devices having the coordinated group in their spare coordinated groups. The base station uses channel state information reported from the user devices of the user device group corresponding to the coordinated group as a basis to perform user scheduling on the coordinated group.
US09544157B1
The illustrative embodiments described herein provide improved systems and methods for conferencing enterprise and non-enterprise callers. In one embodiment, a method includes receiving a first call initiated by an enterprise caller at an enterprise, communicating with an enterprise media server to initiate a tributary conference on the enterprise media server, joining the enterprise caller to the tributary conference such that the enterprise caller is in data communication with the tributary conference, receiving a second call initiated by a non-enterprise caller via a public switched telephone network, interfacing the non-enterprise caller with a data center media server, creating a home conference on the data center media center, joining the second call to the home conference, and interfacing the home conference on the data center media server to the tributary conference on the enterprise media server to form a linked conference between the enterprise caller and the non-enterprise caller.
US09544153B1
A method, system and computer-readable medium for establishing secure connections using compressed cryptographic chaining certificates, the method including receiving a first compact representation corresponding to a certificate for validating a first entity at a second entity, retrieving a local list of one or more compact representations corresponding to one or more certificates locally available to the second entity, comparing the first compact representation to the one or more compact representations within the local list, determining if the first compact representation matches at least one of the one or more compact representations, retrieving the certificate corresponding to the at least one of the one or more compact representations if the first compact representation matches the at least one of the one or more compact representations and validating the first entity using the retrieved certificate corresponding to the at least one of the one or more compact representations.
US09544152B2
A system includes a first computer processor that receives a data transmission from a second computer processor. The data transmission includes a client certificate authentication and a user-based authentication. If the incoming information cannot be authenticated by the client certificate in a first layer of the system landscape, then there is no further data transmission to a second layer. If the first layer can authenticate the client certificate authentication, the system landscape transmits the data transmission to the second layer. If the second layer cannot authenticate the user-based authentication, the system prevents the data transmission from being processed at the second layer. If the second layer can authenticate the user-based authentication, the system processes the data transmission at the second layer.
US09544150B2
A first digital identification document is transmitted from an identification authority to a mobile device of an identified individual. This first digital identification document is digitally signed and includes a set of attributes about the identified individual. In the same manner, a second digital identification document is also transmitted to the identified individual's mobile device. The second digital identification document is also digitally signed but includes a different set of attributes about the identified individual. The identified individual is then confronted by a series of challengers, wherein each challenger requires a different amount of information about the identified individual. Based on the identity of each challenger, the identified individual selects an appropriate identification document and transmits it to the applicable challenger's device. The challenger is then able to confirm both the information he needs about the identified individual and the validity of the identification document that he receives.
US09544141B2
Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
US09544140B1
A hierarchy is defined that includes encryption keys associated with different first and second levels of the hierarchy, where the second level includes fewer of the encryption keys than the first level. The encryption keys of the first level secure a plurality of data objects. The encryption keys of the first level are grouped into key groups that respectively include one or more of the encryption keys of the first level. The one or more of the encryption keys of the first level included in each of the key groups are secured with a respective one of the encryption keys of the second level.
US09544136B2
A network and related methods for transmitting processes in a network secretly and securely is described. The network use keys, through path-key establishment and a key pool bootstrapping, to ensure that packets are transmitted and received properly and secretly in the presence of one or more adversarial nodes.
US09544126B2
Network coding and multiple packet reception (MPR) are used together in a wireless network. In at least one implementation, a novel medium access control (MAC) protocol is provided that enhances throughput in a wireless mesh network that uses network coding and MPR by providing fairness to information flows, rather than fairness to individual nodes.
US09544121B2
A method includes receiving at a receiver circuit a composite signal including non-interfered data resource elements and interfered data resource elements from a plurality of radio cells, and determining a first mutual information metric based on the non-interfered data resource elements. The method further includes determining a second mutual information metric based on the interfered data resource elements, and determining effective mutual information based on a combination of the first mutual information metric and the second mutual information metric.
US09544119B2
An embodiment of the present invention relates to a method of obtaining control information through an enhanced physical downlink control channel (E-PDCCH) by a terminal in a wireless communication system. The method includes performing blind decoding on a common searching space in a set of first resource blocks on a subframe; and performing blind decoding on a terminal-specific searching space in a set of second resource blocks on the subframe, wherein a first start orthogonal frequency division multiplexing (OFDM) symbol of an E-PDCCH resource region including the common searching space in the set of first resource blocks and a second start OFDM symbol of an E-PDCCH resource region including the terminal-specific searching space in the set of second resource blocks are set individually.
US09544117B2
Embodiments provide systems and methods for adaptive reference signal mapping in wireless multi-access communication networks, including LTE, WLAN, WiMAX, Bluetooth, etc. In an embodiment, the reference signal mapping configuration is user equipment (UE) specific and can be configured semi-statically or dynamically according to one or more communication related parameters of the UE. The one or more parameters can include, without limitation, a modulation scheme used for communication with the UE, a modulation and coding scheme (MCS) used for communication with the UE, a distance of the UE relative to the base station, an antenna configuration at the UE, interference management capability of the UE, and a rank of the UE.
US09544115B2
Methods and apparatuses are described for improving identification of reference signal transmissions at a user equipment (UE). One or more restrictions related to reference signal transmissions in one or more interfering signals can be identified. One or more reference signal transmissions received in the one or more interfering signals can then be detected based at least in part on the one or more restrictions. The one or more reference signal transmissions received in the one or more interfering signals can be processed to improve communications with a serving base station.
US09544112B2
Disclosed is a method by which a terminal transmits and receives a signal in a multi cell-based wireless communication system. Particularly, the method comprises the steps of: transmitting, to a serving cell, capability information in which the number of supportable channel status information (CSI) processes is set to zero; receiving, from the serving cell, information on a neighboring cell through an upper layer signal as a response to the capability information; receiving a cell-specific reference signal from the neighboring cell; reporting, to the serving cell, the CSI estimated on the basis of the cell-specific reference signal; and receiving, from the neighboring cell, a user equipment specific reference signal and a data channel on the basis of the CSI.
US09544106B2
Transmission/reception timing of a data signal and a control signal through a Uu interface and transmission/reception timing of the data signal through a Ud interface are properly adjusted. A mobile communication method according to the present invention includes: a step A in which a radio base station eNB notifies a mobile station UE#1 and a mobile station UE#2 that an opportunity to transmit and receive the data signal through the Ud interface is allocated through a PDCCH in which an X-RNTI is used; and a step B in which the radio base station eNB transmit “direction information”, for notifying of a direction in which the data signal should be transmitted in the opportunity, to the mobile station UE#1 and the mobile station UE#2.
US09544101B2
An apparatus and method are provided for a mobile communication system. The method includes generating at least one symbol group to which an orthogonal sequence is applied; determining one of a first antenna set and a second antenna set for mapping the generated at least one symbol group based on the a symbol group index and a physical hybrid automatic repeat request indicator channel (PHICH) group index; mapping the generated at least one symbol group to the determined antenna set; and transmitting the mapped at least one symbol group.
US09544098B2
An information processing apparatus, connected to a management server managing a set value used among a plurality of information processing apparatuses, can perform an appropriate process according to the situation of an information processing system and can prevent wasteful power consumption thereof. A set value acquired from the management server and changed by the information processing apparatus is transmitted to the management server, but when the transmission fails, the transmission of the changed set value is retried, and it is switched according to a classification of the set value to be transmitted whether the retry is stopped or is continued.
US09544090B2
A hard input low density parity check decoder is provided that shares logic between a bit-flipping decoder and a syndrome calculator. The hard-decision decoder decodes one or more error-correcting (EC) codewords and comprises a bit-flipping decoder that flips one or more bit nodes connected to one or more unsatisfied parity checks; and a syndrome calculator that performs a parity check to determine whether the bit-flipping decoder has converged on a valid codeword, wherein the bit-flipping decoder and the syndrome calculator share one or more logic elements. The decoder optionally includes means for updating a parity check equation of each flipped bit. Error-correcting (EC) codewords are decoded by flipping one or more bit nodes connected to one or more unsatisfied parity checks; and updating one or more parity check equations associated with the one or more bit nodes each time the one or more bit nodes are flipped. The parity check equations are updated whenever a bit is updated. The exemplary method terminates based on a predefined syndrome output.
US09544088B2
Disclosed are a broadcast signal transmitter, a broadcast signal receiver, and a method for transceiving a broadcast signal in the broadcast signal transmitter/receiver. A method for transmitting a broadcast signal comprises the following steps: signaling in-band signaling information to at least one of a service component physical layer pipe (PLP) including at least one service component of a broadcast service, a first information PLP including first service information applied to one broadcast service and a second information PLP including second service information applied commonly to a variety of broadcast services; performing the FEC encoding on data included in each PLP; performing time-interleaving on the FEC encoded data; generating a transmission frame including the time-interleaved data; and modulating the transmission frame and transmitting a broadcast signal including the modulated transmission frame.
US09544081B2
A method includes dividing a Time Division Multiple Access (TDMA) structure into a plurality of first time slots and a plurality of second time slots. The first and second time slots are allocated to communications using first and second protocols, respectively. The method also includes communicating with at least one first wireless device using the first protocol during the first time slots. The method further includes communicating with at least one second wireless device using the second protocol during the second time slots.
US09544077B2
A method for transmitting useful information between a transmitting terminal and a receiving terminal connected via a transmission channel. The transmitting terminal defines control information for the useful information, and searches in an association table, which is accessible from the transmitting terminal, for a frame-synchronization word associated with the control information. The transmitting terminal generates a frame of data from the useful information, and transmits, over the transmission channel, a data stream that includes the frame-synchronization word and the frame of data.
US09544073B2
A method includes receiving at least an indication of a notification message through a first channel and receiving at least a part of the notification message through a second channel. The receiving at least an indication of a notification message may include a push-type delivery, and the receiving at least a part of the notification message may include a pull procedure. Alternatively, the receiving at least an indication of a notification message may include a poll-type delivery, and the receiving at least a part of the notification message may include a pull procedure.
US09544066B2
Passive fibre-optic enclosure comprising, a) one or more fibre-optic functional units of a telecommunication network, optically connectable, via an optical fibre, with a central network unit, for receiving telecommunication signals for one or more subscribers via the optical fibre from the central network unit, characterized in that the enclosure further comprises, on the inside of the enclosure, b) transceiving means, which is operable to generate first optical signals using electrical energy, which is operable to receive optical response signals from the central network unit, which is optically connectable to the optical fibre such that the first optical signals can be transmitted by the optical fibre to the central network unit, and such that optical response signals can be transmitted by the optical fibre from the central network unit to the transceiving means.
US09544057B2
The present invention relates to an interconnect structure for coupling at least one electronic unit for outputting and/or receiving electric signals, and at least one optical unit for converting said electric signals into optical signals and/or vice versa, to a further electronic component. The interconnect structure comprises an electrically insulating substrate (102) and a plurality of signal lead pairs (104, 120) to be coupled between said electronic unit (108, 116) and a front end contact region (106) for electrically contacting said interconnect structure by said further electronic component. A ground plane layer (118) is electrically insulated from said pairs of signal leads (104, 120), wherein each pair of signal leads (104, 120) has a circuit connecting region (122) for electrically contacting respective terminals of said at least one electronic unit (108, 116), and wherein in a region adjacent to said terminals of said at least one electronic unit (108, 116) said ground plane layer (118) has a plurality of clearances (126) that are each allocated to one pair of signal leads (104, 120) and separated from a respective neighboring clearance.
US09544056B2
A method of processing a digital signal for transmission is provided comprising digital data frames, by compressing the digital data frames; and generating an optical data unit for transmission comprising multiple of the compressed digital data frames. The optical data unit is configured for transport by an Optical Transport Network, OTN.
US09544055B2
A method for operating an optical network element is provided, wherein based on a quality parameter a subsequent set of parameters is selected to operate the optical network element. Also, an according optical network element and a communication system comprising at least one such optical network element are suggested.
US09544053B2
The invention relates to a method for optimizing the data rate, in a wireless communication system comprising a LED forming an emitting device, and a photodetector forming a receiving device. For a given value of a DC component of the supply signal of the LED, the modulation amplitude of an AC component of this supply signal is adjusted step by step, so as to improve the transmission quality of the signal provided by the LED and received by the photodetector. The invention also relates to an optimization module implementing such a method. Alternatively, the modulation amplitude of the AC component of the supply signal is set, and the value of the DC component is adjusted step by step.
US09544051B2
A method and system for measuring chromatic dispersion, experienced by ASK/PSK modulated optical signals, are provided. Dispersion measurement is enabled either by encoding an additional overhead at lower baud rate or by monitoring signal SOP or RF spectrum of signal SOP. The bulk chromatic dispersion of the link is measured by analyzing the dispersion broadening of the overhead constellation or signal temporal diagram, or time-overlapped signal diagram, or overhead spectrum. This information is used to reduce the computation time required for electronic recovery of a highly dispersed signal.
US09544047B2
An avionics system allows aircraft to introduce bogus “ADS-B Out” messages that are recognized as false only by authorized users. The system enables aircrafts flying at low altitudes to prevent misuse of their ADS-B Out information by maliciously operated cyber and physical attack tools. Aspects of the illustrative embodiment include the system architecture, including an Airborne ATC Processor and Ground ATM System Processor; a process employed by aircraft for generating authorized bogus ADS-B Out messages; a process employed by aircraft for transmitting authorized bogus ADS-B Out messages; and a process employed by air traffic control and other aircraft for decoding the authorized bogus ADS-B Out messages.
US09544046B2
In some embodiments, a first RF signal is received at a wireless repeater, a signal quality is determined based on the first RF signal, the signal quality is analyzed based on a parameter, an operation mode is auto selected based on analysis of the signal quality, and a second RF signal based on the first RF signal is generated for transmission according to the selected operation mode. Under one mode, a first RAC of the wireless may generate data based on a first IF signal downconverted from a first RF signal. Based on the data, a second RAC of the wireless repeater may generate a second IF signal, which can be used to generate a second RF signal for transmission. Under another mode, the first RAC may provide the IF signal to the second RAC, which provides the IF signal for generation of the second RF signal.
US09544038B2
Disclosed are a method, device and system for signalling transmission in a virtual multi-antenna system. The method includes N terminals receive CSI-RSs from a Node B, N being a positive integer larger than or equal to 2; and one terminal in M terminal(s) calculates channel related information from the Node B to the terminal according to the received CSI-RS, and sends the channel related information to L terminal(s), wherein the M terminal(s) form(s) a subset of the N terminals, M is smaller than or equal to N and larger than or equal to 1, and L is smaller than or equal to N and larger than or equal to 1. A first sending unit in the device is configured to calculate channel related information from a Node B to one terminal in M terminal(s) according to a CSI-RS received by the terminal, and send the channel related information to L terminal(s).
US09544036B2
There is provided beam forming using an antenna array configured to transmit across an angular sector. A first set of virtual antenna ports is determined by a mapping of physical antenna ports of the antenna array, the first set of virtual antenna ports defining a beam pattern. A first set of reference signals for acquiring channel state information is transmitted over the first set of virtual antenna ports. Angular information about a wireless transceiver device receiving the transmitted first set of reference signals is acquired. The beam pattern is adapted based on an accuracy of the angular information and/or the angular information itself.
US09544035B2
Transmission quality is improved in an environment in which direct waves dominate in a transmission method for transmitting a plurality of modulated signals from a plurality of antennas at the same time. All data symbols used in data transmission of a modulated signal are precoded by hopping between precoding matrices so that the precoding matrix used to precode each data symbol and the precoding matrices used to precode data symbols that are adjacent to the data symbol in the frequency domain and the time domain all differ. A modulated signal with such data symbols arranged therein is transmitted.
US09544032B2
In one embodiment, a method for transmitting data in a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM)-offset quadrature amplitude modulation (OQAM) system includes selecting a precoding matrix in accordance with a projection of the precoding matrix on a precoding space and generating a precoded modulated pulse shape by applying the precoding matrix to a data vector and a pulse shape. The method also includes transmitting, by a first device to a second device, the precoded modulated pulse shape.
US09544028B2
Technologies and implementations for Doppler frequency shift compensation are generally disclosed.
US09544027B2
A loop-powered transmitter includes a data isolation transformer including primary and secondary windings and an analog-to-digital converter (ADC) to convert a sensor signal to a digital value. The transmitter also includes a first microcontroller coupled between a multi-signal interface of the ADC and only one tap of the primary winding of the data isolation transformer, and a second microcontroller coupled to the secondary winding of the data isolation transformer. The first microcontroller is configured to receive the digital value from the ADC over the multi-signal interface and to provide data indicative of the digital value via a single output data line through the tap of the primary winding of the data isolation transformer to the second microcontroller. Unipolar voltage converters may also be included in the transmitter along with a current limiting resistor for the data isolation transformer to reduce the risk of saturating the data isolation transformer.
US09544021B2
An apparatus for communicating with a portable data carrier comprises a first communication interface, based on wireless data transfer technology, for receiving and/or transmitting data via a first communication channel, and a second communication interface, based on different contactless data transfer technology, for receiving and/or transmitting data via a second communication channel. A first software interface to the first communication interface via which an application program stored in the apparatus can communicate with the first communication interface. The apparatus has a second software interface via which the application program can communicate with the second communication interface, with the communication from the first software interface to the first communication interface, and vice versa, being passed via the second software interface.
US09544020B2
A mobile device includes a transceiver for performing wireless communication, a microprocessor for operating said mobile device, a near field communications (NFC) system for performing wireless communication independent of the transceiver and at a lower amount of power than said transceiver, a contactless front end included in the NFC system for receiving or transmitting signals with an NFC capable device, and a pairing system implemented in the microprocessor for pairing one NFC capable device with another NFC capable device. The pairing system configures the mobile device to receive a tag or a device driver from one of the NFC capable devices that are to be paired with each other; and transfers the tag or a device driver obtained from the tag to the other of the NFC capable devices in order to enable interoperation between the two NFC capable devices.
US09544019B1
The embodiments described herein provide devices and methods to facilitate ripple control communication. Specifically, the embodiments provide devices and methods for decoding ripple control data from ripple signals, such as ripple signals that have been superimposed over power signals used to transmit power. These embodiments provide devices and methods that use band-pass filter, signal multiplier, fast and slow low-pass filters, and accumulate a difference between outputs of these slow and fast low-pass filters. This accumulated difference is then used to decode the ripple control data.
US09544017B2
A system for transmitting communication signals, the system comprising an injector circuit connected to a powered circuit conductor and configured to modulate a power signal with a direct current voltage offset, the direct current voltage offset being within a range that causes approximately 1 percent or less total harmonic distortion of the power signal; and a decoder connected to the powered circuit conductor and a load, the decoder configured to demodulate the direct current voltage offset to control the load. A method for transmitting communication signals, the method comprising modulating a power signal on a powered circuit conductor with a direct current voltage offset, the direct current voltage offset being within a range that causes approximately 1 percent or less total harmonic distortion of the power signal; and demodulating the direct current voltage offset to control a load.
US09544014B2
A pulse generator, which is configured to generate a burst pulse formed by burst oscillation signals oscillated in a predetermined time period, includes a burst oscillation circuit configured to generate the burst oscillation signals of different frequencies; and a control circuit configured to control the burst oscillation circuit so as to select the frequencies of the burst oscillation signals from at least two different frequencies or to stop the burst oscillation signals.
US09544009B2
An input device for switchable use between first and second computer systems. A controller of the input device can execute switching logic to direct a radio transceiver of the input device to switch an operating channel of the radio transceiver to a first channel monitored by the first computer system in response to a first event, and thereby, the input device can be utilized to insert data into the first computer system. The controller can execute switching logic to direct the radio transceiver to switch the operating channel to a second channel monitored by the second computer system in response to a second event, and thereby, the input device can be utilized to insert data into the second computer system.
US09544008B2
Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.
US09544005B2
An adaptable mobile phone case includes a main body, a phone cavity, a rotatable power plug that functions as a stand, a storage compartment, a removable compartment lid with a credit card pocket, a phone charger module, a phone case holder with a hook, a mounting hole, an extension connection port, an external connection port, a removable battery, a plurality of battery LEDs, a communication module, a phone charger lock button, a manual switch charging button, a cable canal, a storage access aperture. The phone case allows easy charging of an installed mobile phone, with an additional battery, can store cables and credit cards, can stand on its own for self-photographs, and supports flexible mounting options.
US09544001B1
A system, method and a computer program product for performing the method are provided. The system includes a communication device installed in a vehicle, wherein the communication device is configured to receive a wireless network broadcast message including target criteria other than a network identifier, and output the broadcast message to a user if the communication device satisfies the target criteria. The method includes determining a current location of a first mobile communication device, and the first device sending a message containing target criteria associated with a target vehicle over a wireless data network, wherein the target criteria does not include a network identifier. The method further includes broadcasting the message containing the target criteria over a geographically-specific area including the current location of the first mobile communication device, wherein only a second mobile communication device satisfying the target criteria will receive and display the message.
US09543986B2
A communication device for uplink transmission with a first type of information and a second type of information includes a demultiplexing circuit, a vector selection circuit, a permutation circuit and a Reed-Muller encoding circuit. The demultiplexing circuit generates a first group of information bits and a second group of information bits according to the first type of information and the second type of information. The vector selection circuit selects code vectors from a predetermined vector set for the first group of information bits and the second group of information bits. The permutation circuit permutes the code vectors according to the first group of information bits and according to the second group of information bits. The Reed-Muller encoding circuit encodes the first group of information bits and the second group of information bits with the permuted code vectors for providing different levels of protection.
US09543984B2
A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.
US09543983B2
A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: sending a read command sequence for reading multiple memory cells so as to obtain multiple first bits; determining whether the first bits have a first error; if the first bits have the first error, executing a first iteration decoding procedure on the first bits so as to obtain multiple second bits, and recording first bit flipping information of the first iteration decoding procedure; determining whether the second bits have a second error; and If the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits according to the first bit flipping information so as to obtain multiple third bits.
US09543979B2
A method for compressing measurement data which is transmitted from sensor control units via a data bus to a primary control unit of a battery management system for vehicles, includes transmitting a rate of change/slope of the measurement data to the primary control unit at a start of measurements. The method further includes transmitting deviations/differences in the measurement data from a current slope, and reconstructing, without loss of information, correct measured values from the rates of change/slope and the received deviations/differences with the primary control unit.
US09543968B2
An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.
US09543966B2
A high-frequency oscillator comprises a reference-frequency generator and a high-frequency generator. The reference-frequency generator generates a variable reference frequency and supplies it to the high-frequency generator. The high-frequency generator comprises a phase-locked loop and generates a high-frequency signal from the variable reference frequency. The phase-locked loop comprises at least one first mixer, a second mixer and several switches. The first mixer, the second mixer and the switches are connected in series. The mixers are connected into the phase-locked loop individually in a selective manner by means of the switches.
US09543960B1
A multi-stage frequency divider includes a cascaded arrangement of first and second integer dividers configured to collectively divide a frequency of a periodic reference signal by an integer amount equal to a product of (2N+1) and (2M+1), where N and M are unequal positive integers greater than two. A duty cycle enhancement circuit is provided, which is synchronized to the periodic reference signal and configured to generate a periodic signal having 2MN+N+M cycles of high followed by 2MN+N+M+1 cycles of low or vice versa, where a duration of each cycle is equivalent to a period of the periodic reference signal. A duty cycle correction circuit is provided as a final stage and is configured to generate a periodic output signal having a uniform duty cycle from the periodic signal generated by the duty cycle enhancement circuit.
US09543952B2
A semiconductor memory device includes a ZQ calibration unit configured to generate an output high level voltage (VOH) code according to a VOH control code obtained from a result of comparing a reference voltage with a first VOH; and an output driver configured to generate a data signal having a second VOH determined by the VOH code. The VOH control code includes a pull-up VOH control code and a pull-down VOH control code and the VOH code includes a pull-up VOH code and a pull-down VOH code.
US09543946B2
A signal processing device includes a detection unit configured to detect an intent to use the signal processing device based on whether the signal processing device is in contact with a subject; and a power supply unit configured to supply power to operate the signal processing device based on the detected intent to use the signal processing device without using a separate ON/OFF switch to supply the power to operate the signal processing device.
US09543945B2
System, method, and apparatus for automatically disabling an appliance to prevent accidental fires. A shut-off system is coupled to a smoke detector. When the smoke detector alarm is activated a signal is sent to the shut off system coupled to a cooking appliance. The shut off system includes a timer and an override mechanism. If the override mechanism is triggered prior to the timer expiring, then the shut off system does not activate. If the override mechanism is not triggered prior to the timer expiring then the shut off system activates and decouples the appliance from its power supply.
US09543940B2
A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead.
US09543937B2
Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.
US09543933B2
A current generator circuit included in a triangle-wave generator circuit in a control circuit includes plural stages of current mirrors connected in parallel with each other. The plural stages of current mirrors are placed so that the sum of output currents output therefrom becomes an output current of the current generator circuit. A switching element that controls the on/off state of a current in accordance with the amount of load current of a DCDC converter is connected to each of the current mirrors.
US09543929B2
An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch.
US09543926B2
A signal processor includes: a first adaptive filter that takes a first signal as input and generates a first pseudo signal; a first subtractor that subtracts the first pseudo signal from a second signal to supply a first differential signal as output; a second adaptive filter that takes the first signal as input to generate a second pseudo signal; a second subtractor that subtracts the second pseudo signal from the second signal to supply a second differential signal as output; a first step size control circuit that generates a first step size used in updating the first adaptive filter in accordance with the relation between the second pseudo signal and the second differential signal; and a second step size control circuit that generates a second step size used in updating the second adaptive filter in accordance with the relation between the first signal and the second signal.
US09543922B2
A mesa-shaped piezoelectric resonator element including a resonator section having a thicker thickness than a peripheral section on the board surface of a piezoelectric substrate formed in a rectangular shape, wherein, when the length of the long side of the piezoelectric substrate is x and the board thickness of the resonator section is t, etching depth y of a level-difference section is set to fulfill a relationship in the following equation, based on the board thickness t. y = - 1.32 × ( x t ) + 43 ± 5 ( % )
US09543921B2
Apparatus and methods for controlling overshoot in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner preventing a series cascade of attenuation units from having a transient attenuation value less than an initial and final value of attenuation, an overshoot condition can be prevented. Control signals transition the attenuation units to a first state of attenuation before they transition attenuation units to a second state of insertion.
US09543918B1
A computing device can utilize one or more sensors to capture data associated with a current environment, state, condition, property, etc. of the device. Based at least in part on the captured data, the current environment, state, condition, property, etc. of the computing device can be determined or identified. Based on the determined/identified current environment, state, condition, property, etc., the computing device can configure the notification intensity level for the device. The device can determine a suitable notification intensity level and set that notification intensity level for the device. An incoming communication received at the computing device while the device is still associated with the determined/identified current environment, state, condition, property, etc. can cause a notification to be outputted at the set notification intensity level.
US09543917B2
The disclosed embodiment may be a parametric equalization hardware that is coupled to computer readable memory software configured to present a command interface to a user and control the equalization hardware to manipulate the frequency, Q, and gain. Additionally, software is configured to simultaneously vary the Q and gain of an equalization curve between two preset values defined by: (1) a high gain and narrow Q (“Fire”); and (2) low gain and wide Q (“Water”).
US09543916B2
An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
US09543909B2
An amplifier includes a variable shunt circuit including a first transistor group and a second transistor group. The first transistor group includes at least one transistor including a first terminal connected directly or indirectly to a voltage-current conversion circuit, a second terminal connected directly or indirectly to a load, and a third terminal connected directly or indirectly to a control circuit. The second transistor group includes at least one transistor including a first terminal connected directly or indirectly to the voltage-current conversion circuit, a second terminal connected directly or indirectly to a power source or a ground, and a third terminal connected directly or indirectly to the control circuit. The amplifier is configured to amplify the input signal under exclusive control from the control circuit on a pair of the at least one transistor of the first transistor group and the at least one transistor of the second transistor group.
US09543902B2
A power amplifier includes: an amplifier; an input matching circuit connected to an input of the amplifier; an output matching circuit connected to an output of the amplifier; and a low-frequency processing circuit connected to the input matching circuit or the output matching circuit, wherein the low-frequency processing circuit includes a first line having a first end connected to the input matching circuit or the output matching circuit, a first shot stub connected to a second end of the first line and including a second line and a first capacitor connected in series each other, and a second short stub connected to the second end of the first line in parallel with the first short stub and including a third line and a second capacitor which are connected in series each other, the first line has a length of λ/8, the second line has a length of λ/4, and the third line has a length of λ/8 with respect to a wavelength λ of a fundamental frequency.
US09543896B2
A low-noise block downconverter (LNB) is disclosed. The low-noise block downconverter comprises a first input module, for outputting a first intermediate frequency (IF) signal after receiving a first polarization signal via a first input end; a second input module, for outputting a second IF signal after receiving a second polarization signal via a second input end; a first output module, coupled to the first input module, for amplifying the first IF signal; and a second output module, coupled to the second input module, for amplifying the second IF signal, such that the LNB selectively outputs a first user signal or a second user signal.
US09543892B1
Certain aspects of the present disclosure provide techniques and apparatus for generating multiple oscillating signals. One example circuit generally includes a first voltage-controlled oscillator (VCO) having a first inductor and a second VCO having a second inductor in parallel with a third inductor, wherein the second and third inductors are disposed inside a loop of the first inductor and may behave as a magnetic dipole. The loop of the first inductor may be symmetrical, and a combined geometry of loops of the second and third inductors may be symmetrical. The coupling coefficient (k) between the first inductor and a combination of the second and third inductors may be small (e.g., k<0.01), due to the symmetrical geometry of the circuit layout. With a smaller k, the first and second VCOs' inductors may be placed closer to one another, thereby reducing an area consumed by the two VCOs.
US09543888B2
In an example, a clamp assembly for a glass on glass solar module for a tracker is included. The assembly has a lower clamp structure characterized by a top-hat shaped rail structure having a length extending from a first end to a second end. In an example, the assembly has an upper clamp structure configured to sandwich a pair of edges of a pair of solar modules with a portion of the lower clamp structure. In an example, the assembly has a locking spacer configured to the pair of edges of the pair of solar modules. In an example, the pair of edges comprises substantially glass material. In an example, the assembly has a pair of key structures configured with the locking spacer. Each of the key structures is affixed to each of the solar modules to physically lock each of the solar modules to the upper clamp structure.
US09543880B2
A rotary machine control apparatus controlling a drive of a rotary machine that has multiple winding groups is provided. The rotary machine control apparatus includes electric power converters in multiple systems, a failure detection portion, and a control portion. An electric power converter has switching elements in an upper arm and a lower arm and converts DC power. The failure detection portion detects a failure of an electric power converter or a winding group. The control portion calculates a current command value and a maximum current limit value, and controls an output to the electric power converter. The control portion stops the output to the electric power converter in a failure system, and the control portion increases the maximum current limit value with respect to the output to an electric power converter in a normal system.
US09543878B2
A drive unit includes: an inverter; an electric motor that has a first winding connected to an output part of the inverter and a second winding connected to the first winding; a first semiconductor switch that has a first end connected to the first winding and a second end connected to the second winding; a second semiconductor switch that has a first end and a second end connected to the first winding and the first semiconductor switch; and a snubber circuit that is provided between the second end of the first semiconductor switch and the first end of the second semiconductor switch and has a capacitor and a diode.
US09543872B2
A control method for a switched reluctance generator employing dual switched-mode power converters does not require a position sensor. In the excitation stage, the upper tube and lower tube of the main switch of a phase in the power converter are switched on, and the phase current is detected. When the phase current rises to a preset threshold, the upper tube or lower tube of the main switch of the phase is switched off, changing the phase of the switched reluctance generator into a zero voltage natural freewheeling state. When the phase current drops to the valley value, the rotor position is the end position of maximum phase inductance of the phase. This rotor position is used as the switch-off position of the main switch of the phase of the switched reluctance generator, and the upper tube and lower tube for the main switch of the phase are switched off.
US09543869B2
Provided herein are a motor control apparatus, an image forming apparatus, an image forming apparatus including the same, and a motor control method, by which position error of a motor and a control value for compensating for the position error are calculated and reflected in feedback control, thereby quickly removing position error of the motor.
US09543868B2
In an apparatus, a first control unit performs current-feedback control, and a second control unit performs torque-feedback control. The torque-feedback control samples values of each output current at phases. The sampled values of each output current at the phases are referred to as phase-related sampled values of the corresponding output current. The apparatus causes the second control unit to sample values of each output current at the predetermined phases while the first control unit is performing the current-feedback control when switching the current-feedback control to the torque-feedback control. The second control unit uses the values of each output current sampled by the first control unit as the phase-related sampled values of the corresponding output current to start the torque-feedback control when the current-feedback control is switched to the torque-feedback control.
US09543866B2
A motor drive controller is for controlling a motor having multiple phases and includes: a comparison reference voltage generator that generates a predetermined constant voltage as a comparison reference voltage; a counter-electromotive voltage comparator that compares the comparison reference voltage with a counter-electromotive voltage of each phase of the motor; and a rotation state detector that detects a rotation state of the motor based on positive/negative polarities of counter-electromotive voltages of other phases with respect to the comparison reference voltage at the time of an occurrence of a zero cross between the counter-electromotive voltage of any one phase and the comparison reference voltage.
US09543852B2
A method is provided for controlling a DC link voltage of a power converter connecting an electric generator of a wind turbine with a power grid. The method includes determining the rotational speed of a rotor of the electric generator. The method further includes determining a strength of harmonic components of the rotational speed of the rotor, wherein the harmonic components have frequency components being different from a fundamental rotational frequency of the electric generator. The method also includes determining a damping reference signal as a function of the determined strength of the harmonic components, and controlling the DC link voltage of the power converter in response to the determined damping reference signal. A corresponding control system is also provided.
US09543850B2
An electronic apparatus and a method of controlling power thereto are disclosed. The electronic apparatus including: a signal receiver configured to receive an input signal; a power supply configured to supply power to elements of the electronic apparatus; a controller configured to controls power supplied to the power supply; and a driving circuit configured to output an ON signal to the power supply in order to supply power to the elements of the electronic apparatus in response to the signal receiver receiving a preset frequency signal while the controller is turned off. Thus, the electronic apparatus is automatically turned on and off by an input signal of a predetermined frequency without a user's manipulation of an additional power switch, and thus, a user's convenience may be improved.
US09543842B2
The present invention relates to a converter for transferring power between a first DC system of DC voltage V1 and a second DC system of DC voltage V2, the converter comprising: —a first AC/DC converter for transforming DC voltage V1 into a first single phase AC voltage V1ac, of frequency ω, root mean square line-neutral magnitude V1acm and angle α1; a second AC/DC converter for transforming DC voltage V2 into a second single phase AC voltage V2ac, of frequency ω, root mean square line-neutral magnitude V2acm and angle α2; and two inductors L1, L2 and a capacitor C, wherein the first terminals of the inductors and capacitor are connected together, the second terminal of inductor L1 and the second terminal of the capacitor C are connected to the first AC voltage V1ac, and the second terminal of inductor L2 and the second terminal of the capacitor C are connected to the second AC voltage V2ac; wherein the value of the capacitor C, inductor L1 and inductor L2 are selected to enable required power transfer and to minimize current in inductor L1, and/or minimize current in inductor L2.
US09543838B2
A switching power converter includes a phase operable to deliver a phase current to a load through an inductor. The phase current has an expected sawtooth or triangular ripple pattern. The switching power converter further includes a measuring unit operable to measure the phase current at two or more different points of a switching cycle during which the phase is turned on over a first interval of the switching cycle and turned off over a second interval of the switching cycle. The switching power converter also includes an analysis unit operable to determine whether the phase is faulty based on the phase current measurements taken at the two or more different points of the switching cycle. A corresponding method of detecting a phase fault in a switching power converter is also provided.
US09543819B2
A flyback converter is provided that includes a base driver for driving a base current into a base of a BJT power switch. The base driver is controlled so as to adaptively vary the base current across at least some of the pulses.
US09543817B2
This invention relates to energy harvesting of electrical energy by the change in a magnetic circuitous permeability path for magnetic lines of force that move through a coil of wire to induce, by Faraday's Law of Electromotive Induction, an electromotive force at the coil winding terminals of an associated coil. An abrupt, substantially instant change generated by a magnet's axial or angular mechanical and magnetic contact or dislocation through instant movement of the magnet by magnetic unlike pole spring back attractive force action with a high permeability stationary hollow or solid magnetic metal core centered in a coil bobbin with a wire wound wire coil providing efficient electrical generation therefrom.
US09543810B2
A semiconductor module includes a switching element, a molded body, and a motor terminal. The molded body having the switching element disposed therein. The motor terminal has a base portion and a connection portion having an insertion hole into which a motor wire is inserted and connected with the winding wire. The connection portion has a cutaway region that defines a slot. The winding wire of the motor and the semiconductor module are connected via the motor wire and the motor terminal, thereby reducing the number of components used for such connection compared with a connection that uses a connector, and achieving a volume reduction of the semiconductor module and a driver device using the same.
US09543809B2
A radial vent composite heat pipe system for cooling and increasing the power density of an electrical machine is provided. The system comprises a plurality of radial vent composite heat pipe assemblies each comprising a slot portion thermally connected to a vent portion. The slot portions are disposable within respective stator slots of a stator core pack of a stator assembly of the electrical machine. The vent portions are disposable within stator vents of the stator assembly. The slot portions absorb heat from the stator coils of the stator assembly and transfer the absorbed heat to the vent portions. The vent portions reject the transferred heat into a cooling air flowing through the respective stator vent, thereby rapidly transferring heat from the respective stator coil to the cooling air flowing through stator vent, and thereby greatly increasing the power density of the electrical machine.
US09543807B2
An electric motor includes a motor housing (1) and a further housing (6), in which electrical and/or electronic components (7) are arranged. A fluid-leading channel circuit is provided for cooling these components (7) and conductively connects the inside of the motor hosing (1) to the inside of the further housing (6).
US09543803B2
A heat circulation pump includes a pump housing (1) with a pump impeller driven by an electric motor. The electric motor is arranged in a motor housing (8) connected to the pump housing (1). A plastic terminal box (12) is fixed to the motor housing (8) and houses electric and/or electronic components of the engine control and electrically connects the motor, a ground contact arranged on the motor housing (8), and a plug or a socket (34) arranged on the outside of the terminal box (12). The ground contact arranged on the motor housing is connected in an electrically conductive manner to a ground contact of the plug or socket (34) and to at least one conductor inside the terminal box (12). The electric connection between the ground contact arranged on the motor housing (8) and the ground contact of the plug or socket (34) is arranged outside of the terminal box (12).
US09543793B2
A radial-winding stator of a motor including a core and eight poles is disclosed. Each pole has a magnetic pole and a pole piece. The magnetic pole is connected to the core and extends outwards from the core in a radial direction. The pole piece is formed at one end of the magnetic pole distant to the core. The pole piece includes a magnetic end face having an arc length along a circumferential direction of the core, as well as an axial height along an axial direction perpendicular to the radial direction. A ratio of the arc length to the axial height is between 2.05 and 10. In another embodiment, the radial-winding stator includes ten or twelve poles.
US09543778B1
Disclosed herein, among other things, are methods and apparatus for recharging hearing aid batteries using a USB adapter. A system includes a hearing assistance device and a battery recharger. The hearing assistance device includes a rechargeable battery, a recharge coil configured to receive power across a wireless inductive link, and charging circuitry configured to control power received by the recharge coil to recharge the battery. The battery recharger includes a device compartment configured to receive the hearing assistance device, a transmit coil configured to transmit power across the wireless inductive link, and a USB adapter port configured to connect to a USB adapter. The USB adapter is configured to provide power to the recharger.
US09543775B2
A battery controller has a holder, a calculator, an acquirer, a calculator, and a controller. The holder holds, at a predetermined time, a value of a received power supplied from an electrical power receiving system to equipment supplied with power from a rechargeable battery. A calculator calculates a difference between a present value of the received power and a last-held value of the received power last-held by the holder at the predetermined time. An acquirer acquires a command value of the received power for each predetermined time period defined by a predetermined time interval. A calculator calculates a limit value of the received power for each time that is shorter than the predetermined time, based on the command value of the received power for each predetermined time period. A controller controls charge and discharge in the rechargeable battery, based on the calculated difference and on the limit value.
US09543774B2
A power source (30, 32) supply circuit (28) is provided in a communication system of protective headgear for supplying a communication system from a power source (30, 32) associated with the protective headgear. The supply circuit (28) includes a boost converter (44) for better utilization of the electric power supplied by the power source (30, 32). Protective headgear is provided with such a supply circuit (28) for supplying the protective headgear. A method is also provided for operating such a supply circuit (28).
US09543773B2
An object is to inhibit a decrease in the capacity of a power storage device or to compensate the capacity, by adjusting or rectifying an imbalance between a positive electrode and a negative electrode, which is caused by decomposition of an electrolyte solution at the negative electrode. Provided is a charging method of a power storage device including a positive electrode using an active material that exhibits two-phase reaction, a negative electrode, and an electrolyte solution. The method includes the steps of, after constant current charging, performing constant voltage charging with a voltage that does not cause decomposition of the electrolyte solution until a charging current becomes lower than or equal to a lower current value limit; and after the constant voltage charging, performing additional charging with a voltage that causes decomposition of the electrolyte solution until a resistance of the power storage device reaches a predetermined resistance.
US09543748B2
A fault protection system for a power system of a dynamically positioned vessel is provided. The power system is separated into two or more power system sections, each including a bus section of a power distribution bus. The bus sections are connected by bus ties in a ring configuration. Each bus section includes a connection to a generator and a connection to a thruster drive of the dynamically positioned vessel. The fault protection system includes a fault isolation system which includes for each power system section a bus tie circuit breaker for breaking the connection provided by the bus tie.
US09543747B2
A method of splicing shielded wire cables includes the steps of providing a first, second, and third shielded wire cable each having a core conductor axially surrounded by a shield conductor which is axially surrounded by an insulative jacket, providing a flexible insulation layer, a flexible conductive layer, and a section of dual wall heat shrink tubing. The first portion of the flexible insulation layer about the joined first, second, and third core conductors, wrapping the flexible conductive layer about the first, second, and third shield conductors, and disposing the flexible conductive layer and portions of the first, second, and third insulative jacket within the section of dual wall heat shrink tubing, thus forming a shielded wire cable splice.
US09543746B2
The present invention is directed to an enclosure for protecting a cable connection. The enclosure includes a sealing member contained within an inner shell. The sealing member is secured around the cable connection by slideably engaging a rigid outer shell over the inner shell. The inner shell has an external topography defining an inner shell profile and wherein the outer shell has an internal topography defining an outer shell profile such that the outer shell profile is similar to the inner shell profile.
US09543743B2
A faceplate assembly is disclosed. The faceplate assembly includes a cover and a backing plate. The cover has at least one hood positioned at an edge of the cover. The backing plate is connected to the cover. The hood creates an opening between the cover and the backing plate to enable cables to be routed therethrough. The backing plate also has an outer edge with a split to enable the backing plate to be installed over pre-installed cables.
US09543725B2
Pliers include a pair of arm members, a pair of handles, at least one interchangeable working jaw and a control mechanism. Each arm member includes two parallel arm plates. The handles are connected to each other for movement of the arm members towards and away from each other. The working jaw is detachably supported in between the arm plates of the associated arm member. The control mechanism includes a retaining spacer, a driving member and a spring biased between the retaining spacer and the driving member. The retaining spacer is positioned in between the arm plates of the arm member. The driving member is movably disposed in between the arm plates of the arm member and has an end knob exposed outside the arm member so that pressing of the end knob of the driving member drives the driving member to be engaged with or disengaged from the working jaw.
US09543722B2
Provided is a connector including a case having an opposing surface facing external device and a flat plate-shaped contact built in the case. The case includes a first opening which is formed at the opposing surface and through which a contact point of the contact to be connected to a connection terminal of the external device protrudes from the opposing surface, a receiver configured to receive a connector for external connection, and a holder configured to hold the contact. The contact includes the contact point which is disposed in the first opening and which is to contact with the connection terminal of the external device, an elastic portion which is disposed in the case and which moves the contact point in a substantially perpendicular direction relative to the opposing surface, a contact portion which is disposed in the receiver and which is to contact with a connection terminal of the connector for external connection, a held portion which is formed between the elastic portion and the contact portion and which is held by the holder in the case, and a connection portion which is formed between the elastic portion and the contact portion and which connects between the contact point and the contact portion in the case.
US09543717B2
A connector comprises an inner conductor (1) and an outer conductor (2); an insulating medium (3) is provided between the inner conductor and the outer conductor, the insulating medium forming an unclosed cavity, and an opening of the unclosed cavity being a port for termination. The inner conductor comprises a first inner conductor (40) and an elastic inner conductor (60), the first inner conductor and the elastic inner conductor being disposed in the unclosed cavity; the elastic inner conductor (60) comprises an elastic member (61) having an inclinedly oriented free end portion (611) and a protrusion (612) projecting towards the first inner conductor (40); in the case where the connector is unterminated, the protrusion of the elastic inner conductor contacts the first inner conductor, and in the case where the connector is terminated, the inclinedly oriented free end portion (611) is moved substantially laterally by a terminating conductor (50) vertically inserted through the port for termination, such that the protrusion (612) is separated from the first inner conductor (40) and the terminating conductor (50) is in contact with the elastic inner conductor (60). The connector solves the problem of a complex connector structure caused by separation of a performance transmission device and an elastic device of a connector in the prior art.
US09543715B2
An electrical device includes a shutter support structure having a return position, at least one blocking position and an open position. A first shutter element is configured to rotate about a first dimensional axis within a predetermined angular range while being translated in two-dimensions between the return position to the open position, each of the two dimensions being orthogonal to the first dimensional axis. A second shutter assembly includes a second shutter element coupled to the first shutter element, the first shutter element allowing the second shutter portion to move in a first direction parallel to the first dimensional axis when the first shutter element is in the open position, the first shutter element being configured to drive the second shutter element in a second direction parallel to the first dimensional axis when the first shutter element is being translated into the return position.
US09543709B2
An insulating body, which can be inserted into a chamber of a plug-in connector housing intended for this purpose, has at least one recess for at least one contact element for connecting to a conductor of a cable or a conducting path of a printed circuit board, and a shielding element for electromagnetically shielding the contact element, wherein the insulating body is formed from at least a first component and a second component, wherein the insulating body contains a cavity having a surface formed from the first component, and wherein the first component contains a dopant through which the surface is provided with a conductive coating forming the shielding element.
US09543704B1
A power adapter includes a body, a plug, and an operation board. The plug is detachably received in and electrically connected to the body. The plug has an engagement slot. The operation board is rotatably received in the body and includes a hook, a pressing portion and a pop portion. The hook latches to the engagement slot to secure the plug to the body. The pressing portion is pressed by external forces. The pop portion is positioned below the plug. When the pressing portion receives an external force, the pressing portion rotates towards the body and drives the pop portion to rotate away from the body, whereby the pop portion pops up the plug from the body.
US09543703B2
An electrical connector assembly includes first and second mezzanine electrical connectors that include respective first and second arrays of electrical contacts. The electrical contacts can be receptacle, or one can be a plug and the other can be a receptacle. Each electrical connector can further include at least one alignment member that cooperate to align the first and second arrays of electrical contacts relative to each other. Each electrical connector can further include at least one orientation member that allows the first and second electrical connectors to mate when in a predetermined orientation relative to each other.
US09543702B2
A connector has a housing (10) with a lock arm (18) and a slider (60) that is movable on the housing (10) between an advanced position and a retracted position. A deflection regulating portion (67) projects from the slider (60) into a deflection space (24) for the lock arm (18) on a rear part of the lock arm (18) when the slider (60) is at the retracted position. The deflection regulating portion (67) is configured to regulate deflection of a lock arm (18). The slider (60) includes an unlocking portion (64) configured to cover a releasing surface of the lock arm (18) from a side opposite the deflection space (24) at the advanced position and has a shape suspended toward the deflection space (24). The unlocking portion (64) presses the releasing surface by receiving an operation force (F) that deflects the lock arm (18) in an unlocking direction.
US09543698B2
A connector has a first housing (21) provided movably in a holder (10) and movements thereof are regulated by locking between resilient locking pieces (15) formed on the holder (10) and locks (23) formed on the first housing (21). In the process of assembling a first device (60) and a second device (70), the first housing (21) and a second housing (40) are connected properly and lock releasing portions (47) resiliently deflect the resilient locking pieces (15) to separate the resilient locking pieces (15) from the locks (23). When locking between the resilient locking pieces (15) and the locks (23) is released, the first housing (21) moves with respect to the holder (10) while being kept properly connected to the second housing (40) as assembly of the first and second devices (60, 70) proceeds.
US09543692B2
A power tap configured to deflect falling material, such as liquid and/or object, from electrical outlets. The power tap includes a housing having an opening to an electrical outlet, and a shelf that extends outwardly from a portion of the housing above the opening when the housing is in an upright position to divert or deflect falling matter away from the electrical outlet. The power tap may be configured as a relocatable power tap, and may be configured for use in a patient care area in compliance with one or more standards for safety and effectiveness of medical electrical equipment.
US09543691B2
A connector including a cavity for stowing a pre-installed sealing member. The sealing cavity is defined by a first or coupler seal cavity formed on the inside surface of a coupler and a second or insert seal cavity formed on the outer periphery of an insert. Relative motion of the coupler and the insert during assembly causes the sealing member to be displaced from a stowed or inactive seal position to an assembled or active seal position.
US09543681B2
A terminal for an antenna connector has a soldering base, two wings, a resilient electric contacting arm, and two pre-pressing elements. The wings are formed on the soldering base, and each wing has an opening. The resilient electric contacting arm is formed on and protrudes from a rear end of the soldering base and has an extension section, a resilient section, and an electronic contacting section. The pre-pressing elements are located respectively in the openings of the wings, pre-press the resilient section of the resilient electric contacting arm toward the soldering base, and limit the resilient section to sway in an extent from an inner upper edge of each opening to the soldering base. The terminal with the pre-pressing elements performs an excellent electrical contacting effect to improve signal transmission of the antenna connector and a corresponding antenna module.
US09543672B2
A terminal block device to which a first wire and a second wire are to be connected includes a terminal block body made of an insulating material, a cover that is made of an insulating material and covers the terminal block body, a shaft member at which a terminal of the first wire and a terminal of the second wire are engaged, a cylindrical relay terminal through which the shaft member is inserted and which is inserted through the cover, a fastening member for fastening the terminal of the first wire and the terminal of the second wire to the relay terminal. The relay terminal includes a first seat surface that is contactable with the terminal of the first wire between the terminal block body and the cover and a second seat surface that is contactable with the terminal of the second wire outside the cover.
US09543666B2
A connecting terminal includes a receiving body, a clamping element configured to clamp a conductor inserted into the connecting terminal against a busbar arranged in the connecting terminal, a first lever arm rotatably mounted on the clamping element, and a second lever arm rotatably mounted on the first lever arm. The second lever arm has an actuation region by way of which the second lever arm can be pivoted. The clamping element can be moved by the first lever arm into a clamping position and into a non-clamping position when the second lever arm is pivoted.
US09543655B2
Provided is an antenna structure which is capable of having sufficient antenna performance even in an antenna having a small cross-sectional area. The antenna of the present invention comprises: a ferrite sheet; and an antenna sheet (flexible printed circuit board) which has a spiral loop antenna pattern. The antenna sheet is folded and the ferrite sheet is inserted therein to form a folded antenna. The folded antenna is configured in such a manner that a longitudinal pattern of the spiral loop antenna pattern is disposed close to a longitudinal centerline portion of the ferrite sheet.
US09543651B2
A near field communication (NFC) antenna including a dielectric substrate, a coil, and a coupling structure is provided. The coil is disposed on the dielectric substrate. The coupling structure includes at least one coupling branch. Two ends of the coupling branch are respectively connected to two different connection points on the coil. The coupling structure is configured to improve the isotropic characteristics of the NFC antenna.
US09543648B2
Techniques of designing an antenna array with antenna units controlled electronically are described. Through controlling the combination of the reflectors in each of the antenna units, a desired antenna pattern is formed, adapting to the environment, and providing reliable and efficient links between two transceivers. According to one aspect of the present invention, a switch (e.g., a diode) is used to couple two reflectors. The diode is controlled to be on or off so that the reflectors are conductively integrated or separated.
US09543622B2
The main object of the present invention is to provide a lithium solid state secondary battery system capable of restoring the decrease of output characteristics of a lithium solid state secondary battery without deteriorating an anode. The present invention attains the above-mentioned object by providing a lithium solid state secondary battery system including a lithium solid state secondary battery and an overdischarge treating unit, wherein an anode active material layer of the above-mentioned lithium solid state secondary battery contains an anode active material and a sulfide solid electrolyte material containing Li, A (A is at least one kind of P, S, Ge, Al and B) and S and having an ortho-composition, and the above-mentioned anode current collector includes a metal.
US09543618B2
An objection is to provide a high performance secondary battery having good flame retardancy and cycle properties. The present exemplary embodiment provides a secondary battery comprising an electrode assembly in which a positive electrode and a negative electrode are arranged to face each other, an electrolyte liquid and a package accommodating the electrode assembly and the electrolyte liquid, wherein the negative electrode is formed by binding a negative electrode active substance comprising a metal (a) capable of being alloyed with lithium, a metal oxide (b) capable of occluding and releasing lithium ions and a carbon material (c) capable of occluding and releasing lithium ions, to a negative electrode current collector, with a negative electrode binder, and the electrolyte liquid comprises a supporting salt and an electrolytic solvent, the electrolytic solvent comprising at least one phosphate ester compound selected from phosphite esters, phosphonate esters and bisphosphonate esters.
US09543616B2
Disclosed is an electrolyte solution for a magnesium rechargeable battery with a high ionic conductivity and a wide electrochemical window compared to the conventional electrolyte solution. The electrolyte solution is prepared by dissolving magnesium metal into the ethereal solution using combinations of metal chloride catalysts. The electrolyte solution can be applied to fabricate magnesium rechargeable batteries and magnesium hybrid batteries with a markedly increased reversible capacity, rate capability, and cycle life compared to those batteries employing the conventional electrolyte solution. Also disclosed is a method for preparing the electrolyte.
US09543610B2
A fuel cell vehicle includes a fuel cell stack, a front side panel, and a fuel gas device. The fuel cell stack includes a plurality of fuel cells, one end and another end, a first end plate, and a second end plate. The first end plate is disposed at the one end. The second end plate is disposed at the another end. The front side panel is connected to side surfaces of the first and second end plates. The side surfaces face forward in a vehicle driving direction. The front side panel includes a first protruding end portion that protrudes from the first end plate outward in a vehicle width direction. The fuel gas device is disposed on the first end plate so as to be covered by the first protruding end portion when seen from a front side in the vehicle driving direction.
US09543606B2
The present invention pertains to a fuel cell with a storage unit (4) for storing hydrogen (Hx), with a proton conductive layer, which covers a surface of the storage unit (4), and with a cathode (7) on a side of the proton conductive layer, which side is located opposite, wherein the storage unit (4) is directly coupled with an anode and/or the storage unit (4) is incorporated in a substrate (1) of a semiconductor. The storage unit (4) is preferably connected to the substrate (1) at least via a stress compensation layer (3).
US09543603B2
In a fuel cell system that includes a fuel cell that generates power in response to an electrochemical reaction between hydrogen and oxygen contained in air, and a compressor that supplies air to the fuel cell, in which an idle stop is executed to stop power generation by the fuel cell when a required load falls to or below a predetermined value, and during the idle stop, air is supplied in accordance with a voltage condition between a cathode and a anode of the fuel cell, regardless of the required load, air is supplied during the idle stop while detecting an air supply amount, and when the air supply amount reaches a predetermined value, the air supply is stopped.
US09543600B2
A fuel cell system that can supply fuel gas appropriately is provided. The fuel cell system includes an injector 23A and an injector 23B which inject fuel gas, and an ECU 50. The ECU 50 adjusts the flow rate of the fuel gas that is injected from the injector 23A by adjusting the valve opening time period and the valve closing time period of the injector 23A, which are repeated alternately, and make at least a part of the valve opening time period of the injector 23B overlap with the valve closing time period of the injector 23A when opening the valve of the injector 23B.
US09543597B2
According to one embodiment, a fuel-cell power generation system includes a fuel cell that generates electricity by electrochemical reaction using fuel and an oxidizer and a resin module that includes a flow path through which fuel, air, or water flows, inner walls defining the flow path being made of resin.
US09543590B2
A catalyst layer composition for a fuel cell includes an ionomer cluster, a catalyst, and a solvent including water and polyhydric alcohol; and an electrode for a fuel cell includes a catalyst layer comprising an ionomer cluster having a three-dimensional reticular structure, and a catalyst, a method of preparing a electrode for a fuel cell includes a catalyst layer comprising an ionomer cluster having a three-dimensional reticular structure, and a catalyst, and a membrane-electrode assembly for a fuel cell including the electrode and a fuel cell system including the membrane-electrode assembly.
US09543589B2
Batteries comprise a carbon fiber electrode construction of the invention and have improved DCA and/or CCA, and/or may maintain DCA with an increasing number of charge-discharge cycles, and thus may be particularly suitable for use in hybrid vehicles.
US09543585B2
Provided is a binder composition for electrodes that has high stability in the form of a liquid composition dissolved or dispersed in a solvent and can improve cycle property of a non-aqueous electrolyte battery. The binder composition used is a binder composition including a polymer A containing 80% by weight or more and 99.9% by weight or less of a repeating unit derived from a monomer including a nitrile group and 0.1% by weight or more and 20% by weight or less of a repeating unit derived from an ethylenically unsaturated compound, wherein a weight-average molecular weight of the polymer A is 500,000 to 2,000,000, and a molecular weight distribution (Mw/Mn) of the polymer A is 13 or smaller.
US09543578B2
A method for manufacturing a negative electrode active material for a secondary battery that uses a non-aqueous electrolyte, including the steps of: depositing silicon according to an electron beam vapor-deposition method with metallic silicon as a raw material on a substrate of which temperature is controlled from 800 to 1100° C. at a vapor deposition rate exceeding 1 kg/hr in the range of film thickness of 2 to 30 mm; and pulverizing and classifying the deposited silicon to obtain the negative electrode active material. As a result, there is provided a method for manufacturing a negative electrode active material of silicon particles as an active material useful for a negative electrode of a non-aqueous electrolyte secondary battery that is, while maintaining high initial efficiency and battery capacity of silicon, excellent in the cycle characteristics and has a reduced volume change during charge/discharge.
US09543576B2
Methods of making high-energy cathode active materials for primary alkaline batteries are described. The primary batteries include a cathode having an alkali-deficient nickel(IV)-containing oxide including one or more metals such as Co, Mg, Al, Ca, Y, Mn, and/or non-metals such as B, Si, Ge or a combination of metal and/or non-metal atoms as dopants partially substituted for Ni and/or Li in the crystal lattice; an anode; a separator between the cathode and the anode; and an alkaline electrolyte solution.
US09543572B2
The present invention provides a non-aqueous electrolyte secondary battery that comprises an electrode body comprising a positive electrode and a negative electrode. The positive electrode has an upper operating voltage limit of 4.5 V or higher relative to lithium metal. The electrode body comprises a lithium titanate-containing layer. The lithium titanate-containing layer is isolated from the negative electrode.
US09543566B2
Miniature electrodes and electrochemical cells are disclosed. Such electrodes are made from forming an electrode mixture onto a current collector and distal end of a feedthrough pin such that the current collector and distal end of the feedthrough pin is encapsulated. The methods and electrode assemblies disclosed herein allow such electrode assemblies to be made free from the step of directly attaching a formed electrode to a feedthrough pin and thus simplifying assembly and decreasing size.
US09543555B2
A battery module including a plurality of unit cells, a plurality of bus bars electrically connecting the plurality of unit cells, a positive electrode terminal and a negative electrode terminal that are electrically connected and in contact with two ends of the plurality of unit cells, a battery housing accommodating the plurality of unit cells and the bus bars, and detection terminals that are respectively electrically connected to the plurality of bus bars, wherein the detection terminals are exposed outside the battery housing. Accordingly, voltage balancing between the unit cells may be controlled without disassembling the battery module.
US09543554B2
A battery holder includes restriction members protruded from a holding base plate in an axial direction of batteries to be located in spaces between the batteries. Each of the restriction members has: a tapered surface which is inclined to the axial direction and is in line contact with an outer periphery of the end face of the battery when the restriction member is inserted into the space, so as to apply a force to move the battery in a radial direction of the battery; and a support surface which supports a side face of the battery that is not in contact with the tapered surface, by surface contact. The support surface receives a moving force in the radial direction from the tapered surface and supports the side face of the battery by a reactive force.
US09543542B2
An organic light-emitting display includes a first substrate which includes a pixel region, and an encapsulation region which surrounds the pixel region, an organic light-emitting device which is located in the pixel region, a sealant which is located in the encapsulation region, and a dummy metal which is interposed between the first substrate and the sealant, where the encapsulation region includes a first encapsulation region and a second encapsulation region which is adjacent to the first encapsulation region, and the dummy metal is located in the first encapsulation region.
US09543540B2
A method of manufacturing an OLED device, a semi-finished product, and a OLED are described herein. In one embodiment, the method comprises providing an electrically conductive carrier substrate with a first carrier surface and a second carrier surface, assembling at least the first carrier surface a patterned layer of insulating material over an integral area, the layer of insulating material being patterned by a plurality of holes such that an electric access to the first carrier surface is possible, assembling a patterned conductive coating on the insulating material such that the conductive coating enters the holes and covers the insulating material, whereby the conductive coating is patterned such that a number of discrete first electrode areas are formed in the conductive coating, applying an organic light-emitting layer above at least one first electrode area, applying a second electrode layer above the organic light emitting layer.
US09543537B2
A method for the application of solution processed metal oxide hole transport layers in organic photovoltaic devices and related organic electronics devices is disclosed. The metal oxide may be derived from a metal-organic precursor enabling solution processing of an amorphous, p-type metal oxide. An organic photovoltaic device having solution processed, metal oxide, thin-film hole transport layer.
US09543532B2
Novel organic compounds comprising a substituted anthracene or acridine ligand are provided. In particular, the compound includes an anthracene ligand substituted at the 9 and 10 positions. The compound may be used in organic light emitting devices to provide devices having improved efficiency and lifetime. In particular, these compounds may be especially beneficial for use in blue-emitting OLEDs.
US09543528B2
A compound for an organic optoelectric device, an organic optoelectric device including the same, and a display device including the organic optoelectric device, the compound including a combination of a moiety represented by the following Chemical Formula I and a moiety represented by the following Chemical Formula II:
US09543516B2
Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
US09543493B2
A thermoelectric semiconducting assembly. Two parallel plates, a first plate and a second plate, are spaced apart. A plurality of pellets are fitted into said first plate and into said second plate, each said pellet comprising a body, a first cap, and a second cap, said body including a silicon material, said first cap and said second cap including an electrically resistive ceramic material, each pellet in said second plate being connected to a pellet in said first plate. Each pellet includes a doped body, wherein half of said pellets are doped with a p-type dopant to form a p-type pellet and half of said pellets are doped with an n-type dopant to form an n-type pellet. Each plate includes p-type pellets and n-type pellets in an alternating pattern, and each p-type pellet in said first plate connects with an n-type pellet in said second plate, and wherein each n-type pellet in said first plate connects with a p-type pellet in said second plate.
US09543484B1
According to one embodiment, a semiconductor light-emitting device includes a semiconductor layer including a first semiconductor layer, a second semiconductor layer, a light emitting layer, a first surface, and a second surface, the light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second surface opposing the first surface; a p-side electrode; an n-side electrode; a p-side pillar; an n-side pillar; a first insulating layer; an optical layer; a second insulating layer; a first layer; a p-side interconnect; and an n-side interconnect. The first layer includes a first lower end portion and a second lower end portion.
US09543481B2
The present invention relates to a primary particle comprised of a primary matrix material containing a population of semiconductor nanoparticles, wherein each primary particle further comprises an additive to enhance the physical, chemical and/or photo-stability of the semiconductor nanoparticles. A method of preparing such particles is described. Composite materials and light emitting devices incorporating such primary particles are also described.
US09543480B2
A ceramic composite for light conversion comprising a solidified body in which crystalline phases of oxides are three-dimensionally entangled and a method for manufacture thereof. A manufacture method of a ceramic composite for light conversion is characterized in that a polishing step is provided in a chemical mechanical polishing (CMP) process applied to the surface of a solidified body with a structure in which an Al2O3 phase and other phases are three-dimensionally entangled.
US09543476B2
A UV light emitting diode and a method of fabricating the same are provided. The light emitting diode includes an active area between an n-type nitride-based semiconductor layer and a p-type nitride-based semiconductor layer, wherein the active area includes a plurality of barrier layers containing Al, a plurality of well layers containing Al and alternately arranged with the barrier layer, and at least one conditioning layer. Each conditioning layer is placed between the well layer and the barrier layer adjacent to the well layer and is formed of a binary nitride semiconductor. The design of the conditioning layer can reduce stress of the active area while allowing uniform control of the composition of the well layers and/or the barrier layers.
US09543474B2
The semiconductor optical device has a chip of semiconductor lamination having a first semiconductor layer of a first conductivity type having a first surface, a second semiconductor layer of a second conductivity type opposite to the first conductivity type having a second surface, and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer, the chip having side surface including a first side surface which is contiguous to the second surface, forms an obtuse angle with the second surface, extends across the second semiconductor layer and the active layer, and enters the first semiconductor layer, and a cracked surface which is contiguous to the first side surface, a first conductivity type side electrode formed on the first surface, and a second conductivity type side electrode formed on the second surface, wherein in-plane size of the semiconductor lamination is 50 μm or less.
US09543473B2
Provided is a self-supporting polycrystalline GaN substrate composed of GaN-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual GaN-based single crystal grains as determined from inverse pole figure mapping by EBSD analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°. There is also provided a light emitting device including the self-supporting substrate and a light emitting functional layer, which has at least one layer composed of semiconductor single crystal grains, the at least one layer having a single crystal structure in the direction approximately normal to the substrate. The present invention makes it possible to provide a self-supporting polycrystalline GaN substrate having a reduced defect density at the substrate surface, and to provide a light emitting device having a high luminous efficiency.
US09543455B2
A cascading regulation system connected to a number of serially connected power sources and uses multiple regulators having different cutoff voltages to provide an output for the local power consumption unit. Each of the regulators is connected to a subset of serially connected power sources and so configured that if the voltage generated at the lowest tap is no longer sufficient for a stable supply to the local power consumption unit, the next higher regulator takes over, and the output voltage drops in small steps reflective of that takeover of the next higher tap. When the voltage generated across a subsection grows, a lower connected tap may take over again, producing a slightly higher output voltage for the local power consumption unit. The cutover steps are chosen such that the output voltage range matches the range given as the acceptable input range for the local power consumption unit.
US09543454B1
A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.
US09543445B2
A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.
US09543432B2
A high voltage LDMOS device having high side source voltage, an n type buried layer and a p type buried layer situated on the interface between a p type substrate and an n type epitaxial layer; a lateral surface of the n type buried layer and a lateral surface of the p type buried layer not in contact, and are distant from one another with a distance, thereby increasing the withstand voltage between the n type buried layer and the p type buried layer; the p type buried layer and the drain overlap at least partially in a vertical direction, enabling the p type buried layer to exert a reduced surface field action on the drain, to increase the withstand voltage of the drain against the source; the source and the body terminal centrally on top of the n type buried layer.
US09543429B2
There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.
US09543428B2
An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
US09543426B2
One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.
US09543424B2
Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).
US09543423B2
In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier.
US09543422B1
A semiconductor device includes a second region of a second conductivity type above a first region of a first conductivity type. A gate electrode has a portion surrounded by the second region via a gate insulating layer. A first electrode, which is separated from the gate electrode, has a portion surrounded by the second region via a first insulating layer. A third region of a second conductivity type is between the first insulating layer and the gate insulating layer. The third region contacts the first insulating layer and has a second conductivity type carrier concentration higher than the second region. A fourth region has a portion aligned with the third region along a first direction. A fifth region of the second conductivity type contacts the gate insulating layer and is aligned with the first portion along a second direction perpendicular to the first direction.
US09543421B2
A semiconductor device includes a semiconductor layer, a plurality of gate trenches, a gate electrode in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, a p+-type collector region, a plurality of emitter trenches formed between the plurality of gate trenches, a buried electrode in the plurality of emitter trenches, and electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches.
US09543418B2
The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant.
US09543416B2
One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.
US09543412B2
A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the first conductivity type is formed. A trench provided with an inner surface having a side wall surface and a bottom surface is formed, the side wall surface extending through the third layer and the second layer and reaching the first layer, the bottom surface being formed of the first layer. A silicon film is formed to cover the bottom surface. A gate oxide film is formed on the inner surface by oxidation in the trench. The gate oxide film includes a first portion formed by oxidation of the silicon carbide substrate, and a second portion formed by oxidation of the silicon film on the bottom surface. Accordingly, a method for manufacturing a silicon carbide semiconductor device having a high breakdown voltage is provided.
US09543410B2
A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a gate structure. The gate structure includes a gate electrode over a gate dielectric, the gate dielectric having a bottom surface in a first plane. A second etch interacts with a first composition and an initial dopant to remove a bottom portion of a first sidewall spacer adjacent the gate structure, such that a bottom surface of the first sidewall spacer lies in a second plane different than the first plane. The removal of the bottom portion of the first sidewall spacer reduces a first distance between a source or drain and a bottom surface of the gate electrode, thus reducing proximity loading of the semiconductor device and improving functionality of the semiconductor device.
US09543406B2
The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
US09543401B2
A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.
US09543399B2
A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.
US09543396B2
A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.
US09543380B2
A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.
US09543374B2
A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.
US09543370B2
An electronic device display may have an array of pixel circuits. Each pixel circuit may include an organic light-emitting diode and a drive transistor. Each drive transistor may be adjusted to control how much current flows through the organic light-emitting diode. Each pixel circuit may include one or more additional transistors such as switching transistors and a storage capacitor. Semiconducting oxide transistors and silicon transistors may be used in forming the transistors of the pixel circuits. The storage capacitors and the transistors may be formed using metal layers, semiconductor structures, and dielectric layers. Some of the layers may be removed along the edge of the display to facilitate bending. The dielectric layers may have a stepped profile that allows data lines in the array to be stepped down towards the surface of the substrate as the data lines extend into an inactive edge region.
US09543369B2
A display device includes a plurality of pixels each including a light emitting region; and a light blocking layer provided on a side of the plurality of pixels on which light is output. In each of the plurality pixels, the light blocking layer has a plurality of openings allowing light from the light emitting region to be output. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located line-symmetrically. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located point-symmetrically.
US09543363B2
A display device includes a first pixel and a second pixel. The second pixel is controlled to emit light in a predetermined range in a first time period and to not emit light in the predetermined range in a second time period during which the first pixel emits light. The first pixel includes a first organic emission layer having a first thickness and the second pixel includes a second organic emission layer having a second thickness different from the first thickness. A resonance pattern is formed in the second pixel to emit light in a melatonin production inhibition wavelength range that corresponds to the predetermined range. The first pixel may emit blue light, green light, red light, or another color of light including white light.
US09543348B2
The present invention relates to a backlight image sensor chip having improved chip driving performance, in which a region other than a pad region, on which a conductive pad is formed, and a sensing region, on which an optical filter is formed, is used as a region for auxiliary driving so that additional functions such as auxiliary power supply, auxiliary signal transmission and auxiliary operation control can be performed, without additional process, in the backlight image sensor chip having a restricted area, thereby improving the chip driving performance.
US09543346B2
An imaging element according to the present disclosure includes: a first pixel and a second pixel each including a light receiving section and a light condensing section, in which the light receiving section includes a photoelectric conversion element, and the light condensing section is configured to allow entering light to be condensed toward the light receiving section; a trench provided between the first pixel and the second pixel; a first light shielding film embedded in the trench; and a second light shielding film provided on part of a light receiving surface of the light receiving section of the second pixel, in which the second light shielding film is continuous with the first light shielding film.
US09543343B2
Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and a photodetector in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate, and the dielectric layer has a recess aligned with the photodetector. The image sensor device further includes a filter in the recess of the dielectric layer. In addition, the image sensor device includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the filter.
US09543339B2
An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.
US09543334B2
A display panel is provided. The display panel includes a substrate including a non-display region containing a thin film transistor, which includes a semiconductor layer; a first insulating layer; a first metal layer; a second insulating layer; a first and second via hole series disposed adjacent to the respective opposite sides of the first metal layer. The first via hole series includes a plurality of first via holes, and the second via hole series includes a plurality of second via holes. A second metal layer includes a first portion and a second portion. The minimum distance between an edge of the first portion and an edge of the first metal layer is a first distance, and the minimum distance between an edge of the second portion and another edge of the first metal layer is a second distance, and the second distance is greater than the first distance.
US09543332B2
An array substrate comprises: a plurality of flexible cushions; and a plurality of signal lines, wherein the signal lines have ends respectively located on the flexible cushions.
US09543326B2
According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
US09543320B2
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.
US09543318B1
An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.
US09543305B2
A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w′), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w′) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.
US09543301B2
Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.
US09543298B1
A method of forming a single diffusion break includes etching rows of fins into a substrate of a structure from a patterned fin hardmask, the remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the structure to expose the fin hardmask. A photoresist layer is disposed over the structure. An isolation region is patterned across the fins to form first and second parallel fin arrays, wherein any remaining photoresist layer has self-aligned edges which are self-aligned with the isolation region. The self-aligned edges are trimmed to expose end portions of the fin hardmask. The exposed end portions are removed. The remaining photoresist layer is removed. A second dielectric fill material is disposed and planarized over the structure to form a base for a single diffusion break (SDB) in the isolation region.
US09543295B2
A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
US09543285B2
A display panel including a plurality of sub-pixel groups arranged repeatedly to form a pixel array. Each of the sub-pixel groups includes a plurality of first pixel units, a plurality of second pixel units and a plurality of third pixel units. Each of the first pixel units includes a first color sub-pixel and a second color sub-pixel, each of the second pixel units includes the second color sub-pixel and a third color sub-pixel, and each of the third pixel units includes the first color sub-pixel and the third color sub-pixel. The first color sub-pixel, the second color sub-pixel and the third color sub-pixel are sub-pixels having three different colors. At least a part of the first pixel units and at least a part of the second pixel units are arranged along a first direction, and the first direction is tilted relative to a column direction of the pixel array.
US09543283B2
An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted on the top surface of the substrate, a zener diode received in the recess, and a reflecting layer formed in the recess and enclosing the zener diode therein.
US09543273B2
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.
US09543269B2
A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.
US09543268B2
A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal surface of an element substrate. A transmission filter element, a reception filter element, connection electrodes electrically coupled to the transmission filter element and the reception filter element, and an insulating layer surrounding the transmission filter element, the reception filter element, and the connection electrodes are disposed on a first principal surface of an element substrate. The insulating layer covers at least a portion of the surface of each of the connection electrodes. Because the portion of the surface of each of the connection electrodes in an exposed state is covered with the insulating layer, the connection electrodes electrically coupled to the transmission filter element and the reception filter element are prevented from separating from the first principal surface of the element substrate.
US09543261B2
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
US09543259B2
A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.
US09543254B2
A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.
US09543253B2
A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.
US09543248B2
An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.
US09543243B2
Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other.
US09543239B2
A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm.
US09543238B1
A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components. The lead frame encapsulates the center semiconductor chip. Each connecting components establishes an electrical connection between the center semiconductor chip and the lead frame. At least one of the center semiconductor chip, the lead frame, and the connecting component forms an indicator.
US09543234B2
A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich layer extends into the opening and contacts the dielectric layer. A tantalum-containing layer is formed over and the contacting the silicon rich layer. An annealing is performed to react the tantalum-containing layer with the silicon rich layer, so that a tantalum-and-silicon containing layer is formed.
US09543231B2
Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.
US09543223B2
A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of a subset of first overlay marks and second overlay marks by determining the differences between the subset of first overlay marks generated in the first layer and corresponding ones of the subset of second overlay marks generated in the second layer.
US09543222B2
An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.
US09543215B2
A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).
US09543214B2
The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
US09543206B2
A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet.
US09543203B1
A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.
US09543196B2
Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.
US09543188B2
The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.
US09543177B2
An object is to prevent the partial pressure of oxidative gas over time in an FOUP mounted on an FIMS system and left open. A surface purge unit is provided on a side opposite to the opening of the FOUP in such a way that wafers supported in the FOUP is located between the opening and the surface purge unit. The surface purge unit ejects inert gas from a plurality of vent holes provided in its surface toward the opening. Uniform purging or replacement of the interior of the FOUP with inert gas can be achieved by creating inert gas flow from an inert gas supply part extending over a surface in the direction from the interior of the FOUP toward the opening along the wafer surface.
US09543175B2
A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof.
US09543165B2
A method for fabricating a semiconductor device includes forming a first hard mask (HM) layer over a material layer, forming a patterned second HM layer over the first HM layer. The patterned second HM layer has first trench extending along a first direction. The method also includes forming a patterned resist layer over the second HM layer. The patterned resist layer has a first line opening extending along a second direction, which is perpendicular to the first direction. The first line opening overlaps the first trench and exposes a portion of the second HM layer. The method also includes etching the first HM layer by using the patterned resist layer and the exposed portion of the second HM layer as an etch mask together to form a first hole feature in the first HM layer.
US09543155B2
A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.
US09543154B2
A method for manufacturing a semiconductor device includes the following steps. A semiconductor substrate is prepared which has a first main surface and a second main surface opposite to each other. The semiconductor substrate is fixed on an adhesive tape at the first main surface. The semiconductor substrate fixed on the adhesive tape is placed in an accommodating chamber. While maintaining a temperature of the adhesive tape at 100° C. or more, a gas is exhausted from the accommodating chamber. After the step of exhausting the gas from the accommodating chamber, a temperature of the semiconductor substrate is reduced. After the step of reducing the temperature of the semiconductor substrate, an electrode is formed on a second main surface of the semiconductor substrate. In this way, there can be provided a method for manufacturing a semiconductor device so as to achieve reduced contact resistance between a semiconductor substrate and an electrode.
US09543153B2
An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.
US09543152B2
The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.
US09543150B2
A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.
US09543149B2
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.
US09543137B2
A sample droplet generator transforms a segmented array of sample material into a continuous stream of droplets containing analytes. The droplets may serve as a sample source for a wide range of detectors and analytical instruments. As one example, the droplets may be introduced into an ion source of a spectrometer that measures ions produced from the droplets or photons emitted from the droplets.
US09543130B2
An internal portion of a photomultiplier tube (PMT) having a reflective photocathode array, and a method for manufacturing the same, are provided. The internal portion of the PMT comprises the reflective photocathode array and at least one dynode structure corresponding to the array of reflective photocathodes. Each reflective photocathode receives light and from the light, generates photoelectrons which then travel towards the at least one dynode structure. Upon the photoelectrons making contact with the at least one dynode structure, the photoelectrons are multiplied.
US09543129B2
An electron multiplier includes an insulating substrate which includes an electrical wiring pattern and in which a through-hole is formed, an MCP arranged on one side of the through-hole of the insulating substrate and electrically connected to the electrical wiring pattern, a shield plate arranged in one side of the MCP and electrically connected to the MCP, an anode arranged on the other side of the through-hole and electrically connected to the electrical wiring pattern, and a signal readout terminal fixed to the insulating substrate for reading a signal from the anode. The shield plate is formed to include the MCP when viewed in a thickness direction. A through-hole exposing at least a portion of the MCP is formed in the shield plate. The insulating substrate, the MCP, the shield plate and the anode are fixed to each other to be integral.
US09543127B2
A method of coating spherical components with a coating process in which the spherical components have a surface area includes positioning the spherical components within a containment boundary on a moving member and positioning the moving member within a chamber. The method includes reducing the pressure within the chamber to less than one atmosphere. The method also includes revolving the moving member about a longitudinal axis. The method further includes oscillating the moving member in a direction of the longitudinal axis and commencing the coating process. The oscillating and revolving produce motion of the spherical components within the containment boundary such that an entirety of the surface area of each component is exposed to the coating process.
US09543120B2
A blanking device for multi charged particle beams includes a plurality of individual blanking mechanisms configured to individually deflect a corresponding beam of multi charged particle beams so as to control ON/OFF of the corresponding beam, and a common blanking mechanism configured to include a plurality of electrode groups, each composed of facing electrodes, where an array pitch of a plurality of electrode groups is smaller than or equal to a pitch of the multi charged particle beams, and to collectively deflect the multi charged particle beams in order to control an exposure time.
US09543113B2
The present invention explains a charged-particle beam device for the purpose of highly accurately measuring electrostatic charge of a sample in a held state by an electrostatic chuck (105). In order to attain the object, according to the present invention, there is proposed a charged-particle beam device including an electrostatic chuck (105) for holding a sample on which a charged particle beam is irradiated and a sample chamber (102) in which the electrostatic chuck (105) is set. The charged-particle beam device includes a potential measuring device that measures potential on a side of an attraction surface for the sample of the electrostatic chuck (105) and a control device that performs potential measurement by the potential measuring device in a state in which the sample is attracted by the electrostatic chuck (105).
US09543112B2
In an existing specimen cryo holder, a change in the orientation of a specimen would lead to tilting of a dewar together with the specimen and hence to bubbling of a cooling source contained in the dewar. In view of this, a specimen cryo holder, including a mechanism capable of cooling a specimen while keeping the posture of a dewar in a fixed direction even when the specimen is tilted into a direction suitable for processing or observation thereof, is provided. Also provided is a dewar in which a vacuum maintenance mechanism is mounted to an outer vessel so that an inner vessel holding a cooling source therein is vacuum-insulated from the outside air.
US09543101B2
An electromagnetic contactor includes: a lower frame having an accommodation space therein; a bobbin having a fixed core, and accommodated in the lower frame; a movable core inserted into the bobbin so as to be moveable up and down; a spring installed between the bobbin and the movable core, and configured to provide an upward restoration force to the movable core; and a ‘b’ contact switch installed at one side of the bobbin, wherein a button for operating a switch lever of the ‘b’ contact switch is provided at a movable core plate positioned above the movable core.
US09543099B2
The present invention relates to a direct current relay, and more particularly, to a direct current relay capable of reducing an electronic repulsive force generated between a fixed contact and a movable contact by a permanent magnet installed to extinguish an arc. The direct current relay includes: a frame; first and second fixed contacts spaced from each other with a predetermined distance there between; first and second magnetic substances formed to enclose a lower part of the first and second fixed contacts; a movable contact movable to contact or to be separated from the first and second fixed contacts, having a first movable contact contactable to the first fixed contact, and having a second movable contact contactable to the second fixed contact; and a pair of permanent magnets installed on long sides of the frame.
US09543096B2
The invention relates to an on-load tap changer for switching among different winding taps of a step transformer without interruption according to the preamble of the first patent claim. The general inventive concept lies in actuating both the selector contact unit and the switching means for uninterrupted load switching by means of a common motor drive without an energy store being connected therebetween.
US09543093B2
A switch actuator device is disclosed. The switch actuator device includes a switch housing, a body having a first and second arm, and a resilient member having a first and second end. The first and second ends of the resilient member are configured to be coupled to the body and switch housing, respectively. The resilient member exerts a first force on the body when the body is at a first position, a second force when the body is at a second position, and a third force when the body is at a threshold position. When the body is rotated about a pivot point from the first to second position, or vice versa, the respective first or second force increases in magnitude and acts on the body to first resist the rotation until the body is in the threshold position, and then assists the rotation.
US09543091B2
A switch unit has a display part that displays an image in at least one input area, a substrate provided above the display part, the substrate having a contact, and at least one substrate opening configured to allow the image in the at least one input area to be viewed from above, an operating button case that covers the substrate, having at least one button case opening, at least one operating button that has translucency, and that is freely pressed down through the at least one button case opening of the operating button case and causes conduction of the contact by being pressed down, light sources mounted on the substrate, that illuminate an area surrounding the at least one operating button, and a light transmissive water-proof sheet made of an elastic member.
US09543079B2
The present invention relates to a production process for an electrode material, an electrode and an electric storage device, and the production process for an electrode material comprises a step of heating a polymer having a silicon-containing unit and a silicon-non-containing unit.
US09543077B2
A separator with a heat resistant insulation layer includes a porous substrate, and a heat resistant insulation layer formed on one surface or both surfaces of the porous substrate and containing at least one kind of inorganic particles and at least one kind of a binder, wherein a content mass ratio of the inorganic particles to the binder in the heat resistant insulation layer is in a range from 99:1 to 85:15, a BET specific surface area of the inorganic particles is in a range from 3 m2/g to 50 m2/g, and a ratio of the moisture content per mass of the binder to the BET specific surface area of the inorganic particles is greater than 0.0001 and smaller than 2.
US09543066B2
A cylindrical superconducting magnet has a number of axially-aligned annular coils of superconducting wire, arranged for cooling by thermal conduction through a cooled surface in mechanical contact with the coils. The coils are provided with a cryogenic radiation shield located between respective radially inner surfaces of the coils and respective axes of the coils. The cryogenic radiation shield is formed of a metal layer in thermal contact with the cooled surface.
US09543065B2
Disclosed is a noncontact power transmission system including a power transmission device for transmitting power to a power receiving device in a noncontact manner. The power transmission device includes a cover covering a portion of an outline of the power transmission device where the power transmission device faces the power receiving device, a base covering another portion of the outline of the power transmission device where the power transmission device does not face the power receiving device, a magnetic body arranged in a space enclosed with the cover and the base, a coil bobbin covering the magnetic body partially or entirely, and a coil wire which is wound around the coil bobbin and which generates a magnetic flux upon receiving an alternating current. The coil bobbin includes a load support.
US09543051B2
System and Method is described that controls the release of contaminated water by rapidly freezing the ground water, including salt water, which permeates the area underneath the a contamination source, so that the resulting ice lens mitigates the extent to which radioactive water is released into the environment. An aperture in the containment area allows the dispersal and dilution of the contaminates by allowing in ground water from outside, and/or removing water from the containment area. The variable aperture may be a physical valve or preferably an opening in the ice shield which size may be controlled by freezing or thawing portions of the ice shield.
US09543044B2
According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
US09543036B2
A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.
US09543032B2
A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first high-voltage using a supply voltage and a second high-voltage using an external voltage which is higher than the supply voltage, and a word line selection circuit configured. The word line selection circuit is configured apply, during a program operation of the memory cell array, the first high-voltage to a selected word line among the plurality of word lines, and the second high-voltage to unselected word lines among the plurality of word lines.
US09543024B2
Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.
US09543023B2
A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.
US09543019B2
Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.
US09543018B2
The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.
US09543016B1
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.
US09543010B2
A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell includes a transistor and a variable resistor. During a specific period, the testing machine provides a write voltage to change the state of the variable resistor. During a maintaining period, the testing machine maintains the level of the write voltage and measures the current passing through the variable resistor. When the current passing through the variable resistor does not arrive at a pre-determined value, the testing machine increases the level of the write voltage. Furthermore, a resistive memory utilizing the testing machine is also provided.
US09542985B2
The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.
US09542983B1
A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.
US09542969B2
When a simple magnification optical system is used in reproduction of a recording medium in which a large number of minute modified regions are three-dimensionally formed inside solid matter, contrast is insufficient and interlayer crosstalk is increased, and therefore, it is impossible to take a sufficient S/N ratio. Provided is a recording medium in which at least one layer is configured by a set of two adjacent sub-layers, and dots on a sub-layer correspond to a recording data ‘1’ and dots on the other sub-layer correspond to ‘0’. These data are played back.
US09542968B1
FePt-based heat assisted magnetic recording (HAMR) media comprising a thick granular FePt:C magnetic recording layer capable of maintaining a single layer film having desirable magnetic properties. According to one embodiment, the thick granular FePt:C magnetic recording layer comprises a plurality of carbon doped FePt alloy columnar grains, where the plurality of carbon doped FePt alloy columnar grains comprise a carbon gradient along the thickness of the hard magnetic recording layer.
US09542963B2
A first adaptive fly height measurement is performed between a read/write head and a recording medium during a stage of qualification testing of a magnetic disk drive. A second adaptive fly height measurement of the read/write head is performed during a subsequent stage of the qualification testing. In response to determining that a fly height decrease between the first and second adaptive fly height measurements is above a threshold value, a mitigation operation is performed to remove a contaminant from a media-facing surface of the read/write head.
US09542960B2
A thermally-assisted magnetic recording head includes a main pole, a plasmon generator, and first and second side shields. The main pole has a front end face located in the medium facing surface. The plasmon generator has a near-field light generating surface located in the medium facing surface. The front end face of the main pole includes a first end face portion, and a second end face portion greater in width than the first end face portion. The first and second side shields have first and second side shield end faces located on opposite sides of at least part of the near-field light generating surface and at least part of the first end face portion in the track width direction.
US09542951B2
An apparatus for processing an audio signal and method thereof, the method including receiving a downmix signal including at least one normal object signal, and a bitstream including object information determined when the downmix signal is generated; extracting, from an extension part of the bitstream, an extension type identifier indicating whether the downmix signal further includes a multi-channel object signal; generating spatial information using the object information and mix information when mode information indicates that the multi-channel object signal is to be suppressed and the extension type identifier indicates that the downmix signal further includes the multi-channel object signal; and transmitting spatial information. The mix information is to control an object position or an object level of the at least one normal object signal.
US09542941B1
In one aspect, devices and methods are disclosed for receiving at least one signal from at least one sensor and, based on analyzing the at least one signal, situationally suspending a necessity of receiving a wakeup word to enable voice command input to a computer.
US09542937B2
A sound processing device includes a noise suppression unit configured to suppress a noise component included in an input sound signal, an auxiliary noise addition unit configured to add auxiliary noise to the input sound signal, whose noise component has been suppressed by the noise suppression unit, to generate an auxiliary noise-added signal, a distortion calculation unit configured to calculate a degree of distortion of the auxiliary noise-added signal, and a control unit configured to control an addition amount by which the auxiliary noise addition unit adds the auxiliary noise based on the degree of distortion calculated by the distortion calculation unit.
US09542933B2
A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.
US09542927B2
A method and system is disclosed for building a speech database for a text-to-speech (TTS) synthesis system from multiple speakers recorded under diverse conditions. For a plurality of utterances of a reference speaker, a set of reference-speaker vectors may be extracted, and for each of a plurality of utterances of a colloquial speaker, a respective set of colloquial-speaker vectors may be extracted. A matching procedure, carried out under a transform that compensates for speaker differences, may be used to match each colloquial-speaker vector to a reference-speaker vector. The colloquial-speaker vector may be replaced with the matched reference-speaker vector. The matching-and-replacing can be carried out separately for each set of colloquial-speaker vectors. A conditioned set of speaker vectors can then be constructed by aggregating all the replaced speaker vectors. The condition set of speaker vectors can be used to train the TTS system.
US09542917B2
A method for extracting the most representative segments of a musical composition, represented by an audio signal, according to which the audio signal is preprocessed by a set of preprocessors, each if which is adapted to identify a rhythmic pattern. The output of the preprocessors that provided the most periodic or rhythmical patterns in the musical composition selected and the musical composition is divided into bars with rhythmic patterns, while iteratively checking and scoring their quality and detecting a section that is a sequence of bars with score above a predetermined threshold. Checking and scoring is iteratively repeated until all sections are detected. Then similarity matrices between all bars that belong to the musical composition are constructed, based on MFCCs of the processed sound, chromograms and the rhythmic patterns. Then equivalent classes of similar sections are extracted along the musical composition. Substantial transitions between sections represented as blocks in the similarity matrices are collected and a representative segment is selected from each class with the highest number of sections.
US09542915B2
Embodiments disclosed herein describe keyless locking tremolo systems and methods for musical instruments that are configured to tune and restrain strings for a musical instrument without an external tool. Embodiments are configured to adjust the vertical positioning of a tightening post and string clamp without an external tool.
US09542902B2
A display device driver that can display images while preventing noise and suppressing display unevenness is provided. When pixel drive voltages corresponding to the luminance levels of respective pixels indicated by a video signal are applied to the data lines of the display device, the pixel drive voltages are applied to data lines that intersect the scanning lines of the display device at positions where the delay time is larger, at timing later than timing of applying the pixel drive voltages to the data lines that intersect the scanning lines at positions where the delay time is smaller, the delay time being a period of time between start of application of the scanning pulse by the scanning driver and actual arrival of the scanning pulse.
US09542894B2
A display apparatus includes: a display unit configured to display an image; a light emission unit configured to individually control light emission for each of a plurality of divided regions; an acquisition unit configured to acquire, for each divided region, a characteristic value of the image displayed on each of the divided regions; and a control unit. The control unit controls light emission of the light emission unit such that: in a moving image region, in which only a moving image is displayed, among the plurality of divided regions, light is emitted at a brightness based on a characteristic value of the moving image region; and in a mixed region, in which both of the moving image and a still image are displayed, among the plurality of divided regions, light is emitted at predetermined brightness.
US09542889B2
A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.
US09542887B2
Organic light emitting display device and method of driving an organic light emitting display device
An organic light emitting diode display device including: a display panel including a plurality of pixels, a scan driving unit configured to supply a scan signal to the pixels via a plurality of scan lines, a data driving unit configured to supply a data signal to the pixels via a plurality of data lines, an emission driving unit configured to supply an emission control signal to the pixels via a plurality of emission control lines, and a timing control unit configured to control the scan driving unit, the data driving unit, and the emission driving unit, and to control the emission driving unit to gradually change an off-period of the emission control signal each time a number of image frames are displayed.
US09542884B2
A display panel includes a display area first and second gate line driving circuits. The display area includes a plurality of pixels is configured to determine how to process a data transmitted on a data line according to first and second control signals transmitted on first and second gate lines respectively and a second control signal transmitted on a second gate line and determine when to emit light according to a light emitting control signal transmitted on a light emitting control line. The first gate line driving circuit is coupled to the first gate line and for providing the first control signal thereto. The second gate line driving circuit is coupled to the second gate line and the light emitting control line and configured to provide the second control signal and the light emitting control signal thereto, respectively.
US09542883B2
A device and a method for controlling brightness of an OLED display device are disclosed.The method for controlling brightness of an OLED display device includes the steps of forwarding external brightness control information in a PWM signal or a brightness control data, selecting and normalizing either the PWM signal or the brightness control data into an external brightness adjusting gain, analyzing a received video data to detect a peak brightness value, multiplying the peak brightness value by the external brightness adjusting gain to produce a final peak brightness value, adjusting the R/G/B maximum gamma voltage values according to the final peak brightness value, and generating R/G/B reference gamma voltage sets by using the R/G/B maximum gamma voltage values adjusted thus.
US09542881B2
A display device includes: a display panel including: a display portion for displaying an image; and a first pad coupled with the display portion and for receiving an out signal from the display portion; a driver coupled with the display portion for supplying a driving signal to the display portion; a cover covering the display panel; and a connection unit coupling the first pad and the driver to each other to transmit the out signal to the driver, wherein at least a portion of the connection unit is in the cover.
US09542879B2
A display panel and a manufacturing method thereof are disclosed herein. The display panel includes a substrate, a peripheral circuit, a plurality of pixel electrodes, a plurality of switches, and an insulating layer. The substrate has a display region and a non-display region. At least a portion of the peripheral circuit is located on the display region of the substrate. The pixel electrodes are located on the display region of the substrate. The switches are respectively and electrically connected to the pixel electrodes, configured to be respectively switched on according to a plurality of scan signals, so as to transmit a plurality of data signals to the pixel electrodes. The insulating layer is located between the peripheral circuit and the pixel electrodes, and is configured to prevent the peripheral circuit from interfering with the pixel electrodes.
US09542873B2
An organic light emitting display comprises: a display panel with a plurality of pixels connected to data lines and sensing lines, each pixel comprising an OLED and a driving TFT for controlling the amount of light emission of the OLED; and a data driver IC comprising a plurality of sensing units for sensing current data of the pixels through a plurality of sensing channels connected to the sensing lines, each sensing unit comprising: a first current integrator connected to an odd sensing channel; a second current integrator connected to an even sensing channel neighboring the odd sensing channel; and a sample & hold unit that removes common noise components from a first sampled value input from the first current integrator and a second sampled value input from the second current integrator while storing and holding the first and second sampled values.
US09542862B2
A dynamically-changeable abdominal simulator system comprises a patient manikin having an abdominal cavity covered by a sheet of synthetic skin, an array of inflatable elements emplaced within the abdominal cavity covering respectively distinct areas of pressurization of the abdominal cavity and supplied with pressurized medium under separate and independent inflation control for each of the inflatable elements in order to simulate a wide range of abdominal ailments and/or conditional expressions thereof. An inflation manifold and an electronic control module operable therewith control the supply of pressurized medium to the inflatable elements. The electronic control module can communicate with an external computer that provides a graphical user interface (GUI) for the user to control the training simulation routines to be performed on the manikin.
US09542861B2
Medical training kits and methods include a simulated liquid blood which simulates mammalian whole blood and a simulated hemostatic component. The simulated liquid blood includes a gellable component, and a simulated hemostatic component includes a gelling agent. The gelling agent causes the gellable component in the simulated liquid blood to form a mass of semi-solid or solid material in response the simulated blood being brought into contact therewith to thereby simulate blood clotting. In certain embodiments, the gellable component is chitosan and/or an alginate compound and the gelling agent is at least one compound which causes the gellable component to desolubulize, polymerize, complex, precipitate, cross-link and the like so as to form a semi-solid or solid mass of chitosan in response to physical contact between the simulated blood and the simulated hemostatic agent.
US09542856B2
A system and method are presented for learning call analysis. Audio fingerprinting may be employed to identify audio recordings that answer communications. In one embodiment, the system may generate a fingerprint of a candidate audio stream and compare it against known fingerprints within a database. The system may also search for a speech-like signal to determine if the end point contains a known audio recording. If a known audio recording is not encountered, a fingerprint may be computed for the contact and the communication routed to a human for handling. An indication may be made as to if the call is indeed an audio recording. The associated information may be saved and used for future identification purposes.
US09542854B2
A system and method of communication based on the Reverse Multiple-Choice Method of teaching and testing is disclosed where at least one communicant is a machine. The method is applicable for training a machine for knowledge engineering and artificial intelligence oriented applications, as well as for a trained machine to assist a human being engaged in the activity of teaching or testing.
US09542837B2
A control method of a gateway communicating with at least one sensor and a service server is provided. The control method may include receiving, from the at least one sensor, first information comprising at least one of bioinformation, disaster prevention information, and public information, transmitting the first information to the service server when the first information meets a first standard, or processing the first information in a data format of the first standard and transmitting the processed first information to the service server when the first information does not meet the first standard, receiving, from the service server, a control command to control the at least one sensor, and transmitting the control command to a sensor corresponding to the control command.
US09542835B2
A pest control device system includes a plurality of pest control devices and a data collector. The system may further include the data collector in the form of a gateway that is connected to a data management server via a computer network along with other gateways in corresponding pest control device groups. Each pest control device includes a pest sensor and a wireless communication circuit to transmit information from the corresponding sensor. The devices also configure to define a local wireless communication network that can relay the information from one to the next and ultimately to the data collector.
US09542828B1
A device, system, and method for evaluating compliance with a hand hygiene standard using acceleration measurements of the hand or wrist. The method is based on the scalar quantities vigor and/or rocking angle.
US09542826B2
In some embodiments, a method includes establishing a communications link between a computing device and an adapter. The adapter is configured to receive at least a portion of a medicament delivery device. A wireless signal is received to maintain the communications link. A relative position between the computing device and the adapter is determined. An alarm is produced when the wireless signal is not received within a time period. The alarm is based on the relative position between the computing device and the adapter.
US09542816B1
A wearable alert device includes an audio transducer and driver circuit that allows selection of either a high or low volume setting for driving the transducer. The driver circuit is operable in a single ended mode for low volume and a double ended mode for high volume. The single ended mode holds one terminal of the transducer low while the other is driven in correspondence with a clock signal, while the double ended mode drives one terminal in correspondence with the clock signal and the other terminal is inverted from the clock signal. The transducer is activated in response to an alert event, and can be driven according to a profile or pattern.
US09542814B2
A gaming system for providing a poker game with a playing card nudge feature.
US09542811B2
A gaming device having a bonus scheme, wherein the player may choose when to play a bonus scheme, so long as the player is qualified to do so. The method of qualifying the player to enter the bonus round connects or links the base game operation of the gaming device with the bonus scheme. The reels of the base game contain symbols which alone or in combination with other symbols yield one or more bonus awards to a player. The bonus awards are escrowed and displayed a bonus award escrow display. Once the player obtains a single bonus award, the player becomes eligible or qualified to play the bonus round and the player may choose to do so at any time. The player can accumulate bonus awards and use multiple bonus awards at one time.
US09542802B2
Various methods and apparatus related to gaming are described. Some embodiments relate to a multi-tiered game involving multiple participants. Some embodiments relate to players from a plurality of gaming operators playing games with one another. Other embodiments are described.
US09542800B2
A method, apparatus, and computer readable storage medium for implementing a bonus round of a slot machine game. A plurality of concealed elements are displayed, and a player can reveal each element one by one, until a terminating symbol is revealed. Combinations are formed and a player is awarded a highest combination upon revealing a terminating symbol.
US09542794B2
A gaming system for playing a wagering game comprises at least one display adapted to display a plurality of reels having symbols. The symbols indicate a randomly selected outcome of the wagering game. The plurality of reels includes at least one single-symbol reel and at least one multi-symbol reel. The at least one display is adapted to display at least one payline overlapping at least one symbol from the at least one single-symbol reel and at least one symbol from the at least one multi-symbol reel.
US09542786B2
A coin hopper includes a rotating disc having recesses that receive and hold coins one by one; a moving body that is disposed at a position corresponding to the recess and moves reciprocally between a holding position and a push-out position; a cam groove including a first route having a substantially circular shape and a second route connected to the first route at first and second branch points and protruding toward the outer periphery of the rotating disc with respect to the first route; and a cam follower disposed in the cam groove provided on a back side of the moving body. The moving body is held at the holding position when the cam follower moves along the first route and moves reciprocally between the holding position and the push-out position when the cam follower moves along the second route.
US09542783B2
An electronic system utilizes a method (500) for authenticating access to a multi-level secure environment. According embodiments, the system stores (501) fingerprint data for at least one authorized human user of the system. The fingerprint data for each authorized user includes copies of fingerprints for two or more fingers of the user. Some time after storing the fingerprint data, the system senses (503) one or more fingers of an individual who is attempting to use the system and compares (505) the sensed finger data to the stored fingerprint data. When at least some of the sensed finger data matches copies of fingerprints in the stored fingerprint data, the system determines (509) a quantity of matching fingerprints. The system then determines (525) a security level for the individual based on the quantity of matching fingerprints and provides access (527) to particular functionality of the system based on the determined security level.
US09542779B2
Embodiments of the invention include a method inserting a new face in a polygonal mesh comprising receiving an input corresponding to: a polygonal mesh having a plurality of faces, a selection of a face (fm) of the plurality of faces, a direction vector (d), a modified target plane (pm), and a threshold angle θ. For each edge (e) of the selected face fm, the method further includes determining each adjacent face (fadj) to selected face fm, and inserting a new face at edge e if no adjacent face exists or if fadj is substantially parallel to pm and within threshold θ. In some embodiments, the new face has a normal orthogonal to e and d.
US09542774B2
Determining a node path through a node graph includes modifying the node graph in accordance with a predetermined platform performance, performing a path finding process through the node graph to obtain the node path, determining if the platform performance has changed, adjusting the node graph to compensate for a change in the platform performance, and re-performing the path finding process through the adjusted node graph to obtain the node path.
US09542772B2
A virtual endoscope image is generated based on an opacity template in which a pixel value of a three-dimensional image is associated with an opacity, the opacity template being capable of showing both of an inner wall of a large intestine region and an inner wall of a residue region present in the large intestine region on the virtual endoscope image, a viewpoint set in the vicinity of a boundary between a space region and the residue region in the large intestine region, a set surface set at a position separated by a previously set distance in a previously set line-of-sight direction from the viewpoint, and a pixel value on a light beam vector beyond the set surface among pixel values of the three-dimensional image on the light beam vector extending from the viewpoint.
US09542767B2
Computer-generated images are generated by evaluating point positions of points on animated objects in animation data. The point positions of the points are used by an animation system to determine how to blend animated sequences or frames of animated sequences in order to create realistic moving animated characters and animated objects. The methods of blending are based on determining distances or deviations between corresponding points and using blending functions with varying blending windows and blending functions that can vary from point to point on the animated objects.
US09542765B2
A method, system and computer program product for virtually placing an object on an image of a human appendage is provided. First, image boundaries are detected in the image of the appendage and converted into a set of line segments. A pair of line segments is evaluated according to a function that combines subscores of the pair of line segments to produce a score. The subscores of the line segments are computed based on various properties such as orientation difference, extent, proximity to the center of the image, bilateral symmetry, and the number of skin-colored pixels. A pair of line segments with the highest score is chosen as the appendage boundaries and is used to determine the position, orientation, and extent of the object. The image of the object is then transformed according to the determined parameters and combined with the image of the appendage to produce the desired result.
US09542760B1
Devices, systems and methods are disclosed for preprocessing JPEG images to enable parallel decoding and for parallel decoding of JPEG images. A JPEG image may be preprocessed to enable parallel decoding by embedding restart (RST) markers within the JPEG data and embedding information in an application (APPn) marker, which may be included in a header associated with the JPEG data. Using the RST markers and information included in the APPn marker, a device may separate the JPEG data into sections and decode the sections in parallel using multiple cores to reduce a time between acquiring and rendering the JPEG image. The parallel outputs may be stored to identified locations in a buffer so that the finished outputs are sequentially stored as a complete decoded JPEG image.
US09542758B2
An image processing apparatus is provided including a storage unit for storing relationships of color coordinates between a plurality of reference colors under each of a plurality of different light sources for each light source, with respect to the plurality of reference colors set in a color space and being different from one another; and a calculation unit for detecting color coordinates of the plurality of reference colors from an object image to be processed, and identifying a light source used in capturing of the object image according to a similarity between relationships of the detected color coordinates and the relationships of color coordinates stored in the storage unit for each light source.
US09542749B2
Fast general multipath correction in time of flight imaging is described, for example, to obtain accurate depth maps at frame rate from a time of flight camera. In various embodiments accurate depth maps are calculated by looking up corrected depth values stored in a look up table. In various embodiments the corrected depth values are highly accurate as they take into account three or more possible light ray paths between the camera and a surface in a scene being imaged. In an example accurate depth maps are computed at a frame rate of a time of flight camera. In an example accurate depth maps are computed in less than 30 milliseconds for an image having over 200,000 pixels using a standard CPU.
US09542736B2
A system may be configured to calculate and use image sharpness results. In some example embodiments, a content-aware image sharpness evaluation scheme is implemented by the system to calculate the degree of sharpness or blur of photographs taken of objects of interest. In certain example embodiments, a calculated sharpness score from the image sharpness evaluation scheme is converted into a score that is meaningful relative to other photographs of the same category as the object depicted in the photograph. In various example embodiments, a mobile-based assistant is configured to provide instant (or near instant) feedback to users uploading photographs using a mobile device. In alternative example embodiments, a web-based assistant is configured to provide instant (or near instant) feedback to users uploading one or more photographs simultaneously to an electronic commerce or marketplace website.
US09542733B2
An image processing method includes: a generating step of generating a cumulative histogram of density values of pixels included in at least each of a first image and a second image; a calculating step of calculating a distance between a density value on a first histogram generated from the first image and a density value on a second histogram generated from the second image, in a space defined to include histogram frequencies of the cumulative histograms and the density values; and a determining step of determining a correspondence relation between the density values included in the first image and the density values included in the second image based on the calculated distances between the density values, and determining a conversion function for correcting a density value between the first image and the second image based on the determined correspondence relation.
US09542732B2
The present disclosure provides a multi-stage image mapping mechanism for mapping a distorted image to a rectified image. For example, the multi-stage image mapping mechanism can remove homography from a distorted image to reconstruct a rectified image in two-stages: (1) a first stage in which distortion is partially removed from a distorted image to generate an intermediate image, and (2) a second stage in which residual distortion is removed from the intermediate image to recover the rectified image.
US09542724B1
To provide smoothly scaleable map features on interactive digital maps, a first and a second sets of style parameters for rendering a map feature at a first zoom level and a second zoom level, respectively, are received. The first and second sets of style parameters are provided to a vertex shader. The vertex shader is configured to interpolate the first set of style parameters and the second set of style parameters to generate an interpolated set of style parameters for a certain zoom level between the first zoom level and the second zoom level, and render the map feature at the certain zoom level in accordance with the interpolated set of style parameters.
US09542723B2
Aspects of the technology pertain to geographical image processing of time-dependent imagery. Various assets acquired at different times are stored and processing according to acquisition date in order to generate one or more image tiles for a geographical region of interest. The different image tiles are sorted based on asset acquisition date. Multiple image tiles for the same region of interest may be available. In response to a user request for imagery as of a certain date, one or more image tiles associated with assets from prior to that date are used to generate a time-based geographical image for the user.
US09542721B2
The display control device has a register for holding mode data for giving: a direction about which of a first display mode for performing display control of display data supplied together with a display timing signal from outside, and a second display mode for performing display control of display data written in RAM without accepting supply of a display timing signal from outside to select; and a direction about whether or not to select a scale-up mode for scaling up the display data, so that the mode data can be rewritten from the outside. The display mode is controlled based on the setting values on the register. The control register can be rewritten according to the type of data to be displayed, the system working situation, user settings, etc. Therefore, the low power consumption allowable in terms of system, and a required display performance can be obtained timely and readily.
US09542716B1
A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster patter.
US09542712B2
A method and system are disclosed for providing a near-real-time measurement of sentiment and advocacy associated with user interactions within a social media environment. A first and second set of social media data, respectively associated with a first and second set of social media interactions, are processed to generate a first and second set of social network advocacy (SNA) data in near-real-time. The resulting first and second sets of SNA data are then processed to generate a first and second set of SNA Pulse (SNAP) metric data, which respectively indicate a near-real-time measurement of sentiment and advocacy for a given aspect of an organization. The first and second sets of SNAP metric data are then processed to generate a set of SNAP metrics differential data, which indicates a corresponding improvement or decline in sentiment or advocacy.
US09542707B2
A computer-implemented method and system for keyword bidding in a market cooperative are disclosed. A particular embodiment includes receiving a keyword bid from a first party; determining a value to a host associated with the keyword bid; augmenting the keyword bid by an amount corresponding to the value to the host; and sending the augmented keyword bid to a second party.
US09542702B2
The present invention relates to a method of raising funds for an organization. In one embodiment, the organization distributes a solicitation to a buyer, or for delivery to a buyer by way of a child relative of the buyer. The solicitation comprises an offer to sell a jewelry article made from a processed exfoliated deciduous tooth of the child, set in a jewelry object, as a gemstone would be set. The buyer sends a payment for the jewelry article to the manufacturer, who sends a payment to the organization for having distributed a solicitation that was converted into a purchase. The buyer sends the exfoliated deciduous tooth to the manufacturer. The deciduous tooth is specially processed in a manner that allows it to be set in the buyer's selected jewelry object as a gemstone would be set to create the completed jewelry article.
US09542690B2
The systems and methods of the disclosure allow user from various countries to take advantage of offers when they are traveling internationally. Once the purchase associated with the offer is made, the transaction information may be processed by the system, such that, the credit and debit associated with the purchase are transmitted to the transaction account and the merchant. The transaction information may be further processed to determine whether the particular transaction is eligible for a reward. Where the transaction is eligible for a reward, the credit and debit associated with reward are transmitted to the transaction account and the sponsoring entity. The reward may be provided in any suitable currency or in various currencies based on the parameters governing the reward offer.
US09542686B2
An integrated system for managing changes in regulatory and nonregulatory requirements for business activities at an industrial or commercial facility. Application of this system to environmental, health and safety activities, and to food, drug, cosmetic, and medical treatment and device activities, are discussed as examples. The system: provides one or more databases that contain information on operations and requirements concerning an activity or area of business; receives information on regulatory and nonregulatory changes that affect operations of the business; converts these changes into changes in data entry forms, data processing and analysis procedures, and presentation (by printing, electronic display and/or distribution) of data processing and analysis results to selected recipients, without requiring the services of one or more programmers to re-key and/or reformat the items affected by the change; and implements receipt of change information and dissemination of data processing and analysis results using the facilities of the Internet.
US09542685B2
A wearable device includes a wearable device structure at least partially made of a silicone rubber. A support member is at least partially positioned in the wearable device structure. ID circuitry is at least partially positioned and coupled to the support. One or more batteries coupled to the ID circuitry.
US09542682B1
A card registry system is configured to automatically identify financial card information in one or more credit files associated with a consumer and populate a card registry account of the consumer with the identified financial card information. Once the financial card information has been obtained from the credit file(s), the card registry system may transmit cancellation and/or reissuance requests to the respective card issuers in the instance that one or more cards are compromised, so that the financial cards may be easily and efficiently cancelled and/or reissued at the request of the consumer.
US09542680B2
An information processing apparatus includes: processing sections that have respective identification information and that perform processing corresponding to a request from another information processing apparatus; and a reporting section that stores the respective identification information of the processing sections and, instead of the processing sections, that reports the identification information to the another information processing apparatus in response to a request for reporting the identification information, the request being issued from the another information processing apparatus.
US09542664B2
A stock monitoring system, for monitoring items of stock in one or more storerooms, includes a portable device including a first processor and a first wireless transceiver for short-range communication. The first processor is operable for receiving a user ID of a second user via the first wireless transceiver and transmitting to the remote system via a second wireless transceiver, at least item data, associated with the user ID. An intermediate unit includes a second processor and a reader and a wireless transmitter adapted for short-range communication. Upon reading the user ID from an ID card of the second user by the reader, the user ID is transmitted via the wireless transmitter, e.g. for a predetermined period. The first processor receives a user ID of a second user via the first wireless transceiver. A method, portable device and intermediate unit are also disclosed.
US09542662B2
Implementations of the present disclosure include methods for providing transparency in streaming event data. In some implementations, methods include receiving a plurality of events, each event comprising event data and being generated by an event source in response to a real-world activity, processing the plurality of events using one or more complex event processing (CEP) rules to generate a complex event, in response to generating the complex event, generating at least one lineage event that comprises lineage information, the lineage information comprising information corresponding to one or more source events, each of the one or more source events contributing to the complex event, and storing the lineage event and the one or more source events in an event archive provided as a computer-readable storage medium.
US09542653B1
LPR instances around physical locations and license plate numbers associated with a person of interest are analyzed to predict the relative likelihood of locating the person of interest at a particular location. An LPR information query includes an indication of a physical location and a license plate number associated with a person of interest. The relative likelihood of locating a person of interest at a particular location at a future point in time is determined based on the LPR instances received. In one example, the relative likelihood of locating the person of interest is based on the relative value of clusters of LPR instances around physical locations associated with the person of interest. Additional license plate numbers are associated with a person of interest based on their appearance within a search zone and time window of LPR instances of a license plate number already associated with a person of interest.
US09542642B2
This application discloses a neural network that also functions as a connection oriented packet data network using an MPLS-type label switching technology. The neural network uses its intelligence to build and manage label switched paths (LSPs) to transport user packets and solve complex mathematical problems. However, the methods taught here can be applied to other data networks including ad-hoc, mobile, and traditional packet networks, cell or frame-switched networks, time-slot networks and the like.
US09542631B2
The dual frequency RF identification device comprises an HF antenna for receiving an HF electromagnetic field, an HF interface, an UHF antenna for receiving an UHF electromagnetic field, an UHF interface, non-volatile memory means formed by a first non-volatile memory and a second non-volatile memory. The first non-volatile memory can be in an active state without the second non-volatile memory being powered and consumes substantially more power than this second non-volatile memory. The first non-volatile memory comprises all data needed for a device configuration allowing this device to carry out at least a communication mode of an UHF protocol, this communication mode having access to the first non-volatile memory but not to the second non-volatile memory. The first non-volatile memory further comprises all attributes needed for a configuration of this communication mode.
US09542627B2
An improved system and methods for identifying, assessing, obtaining, evaluating, processing and displaying information about specific topics of interest. In certain embodiments, information is processed with advanced computation and analytical techniques in which detailed statistical data is generated and refined to produce meaningful quantitative and qualitative information that may be useful in analyzing the economic performance of specific businesses or geographical regions of interest.
US09542618B2
The inventive data processing system and method enable recognition, matching, and/or identification of images and/or of objects, utilizing at least one novel pleographic data processing technique.
US09542614B2
A soft, weighted constraint imposed upon image locations can be used to provide a more accurate segregation of an image into intrinsic material reflectance and illumination components. The constraint is arranged to constrain all color band variations between the image locations into one integral constraining relationship.
US09542609B2
Methods and systems for training a parked vehicle detector. Video data regarding one or more parking sites can be captured. Positive training samples can then be collected from the video data based on a combination of one or more automated computing methods and human-input auxiliary information. Additionally, negative training samples can be collected from the video data based on automated image analyses with respect to the captured video data. The positive training samples and the negative training samples can then be used to train, re-train or update one or more parked vehicle detectors with respect to the parking site(s) for use in managing parking at the parking site(s).
US09542601B2
A system that incorporates teachings of the subject disclosure may include, for example, a processor that can detect an event, access location information for a group of mobile communication devices that are each automatically capturing images, and identify a subset of the group of mobile communication devices that are in proximity to the event based on the location information. The processor can provide first image analysis criteria to the subset of the group of mobile communication devices without providing the first image analysis criteria to remaining devices of the group of mobile communication devices where the first image analysis criteria includes first characteristics associated with an object. The processor can receive a first target image that includes the object from a first mobile communication device of the subset of the group of mobile communication devices. Other embodiments are disclosed.
US09542576B1
A helical physical unclonable function is disclosed. The helical physical unclonable function may be used to authenticate a supply item for an imaging device. Measurements of the magnetic field above a helical flight are stored in a non-volatile memory to be used by an imaging device to authenticate the supply item. Other systems and methods are disclosed.
US09542564B2
A request, from a requester, is received to view user information on a user's personal site associated with a user. A relationship is determined between the requester and the user. User information is provided to the requester based on the requester's relationship to the user.
US09542556B2
A potential malware sample is received from a security device at a server associated with a security cloud service. The sample is executed in a sandbox environment on the server, including by monitoring interaction of the sample with an application program interface (API), provided by the sandbox environment, in order to obtain an API log. It is determined whether the sample is associated with a known malware family including by determining, based at least in part on the API log, if the sample created an executable file and if the sample registered the executable file in a run key. If it is determined that the sample is associated with a known malware family, then an alert is generated.
US09542555B2
A system and method for detecting malware in compressed data. The system and method identifies a set of search strings extracted from compressed executables, each of which is infected with malware from a family of malware. The search strings detect the presence of the family of malware in other compressed executables, fragments of compressed executables, or data streams.
US09542554B1
Detecting duplicate malware samples is disclosed. A first guest clock is set to a first value in a first virtual machine instance. A first malware sample is executed in the first virtual machine instance. A second guest clock value is set to the first value in a second virtual machine instance. A second malware sample is executed in the second virtual machine instance. A determination is made as to whether the first malware sample and the second malware sample are the same, based at least in part on performing a comparison of attempted external contacts generated by executing each of the respective first and second malware samples.
US09542549B2
A method including receiving a request to connect to a single sign-on site, a non-single sign-on site, a system, a mainframe, or to use a mainframe or user device application; determining, by a toolbar of a user device, whether a user is authorized to connect to, initiate, or use the single sign-on site, the non-single sign-on site, the system, the mainframe, the mainframe or user device application; selecting, by the toolbar, one or more user credentials to allow the user to connect to, initiate, or use the single sign-on site, the non-single sign-on site, the system, the mainframe, the mainframe or the user device application when it is determined that the user is authorized; and signing-on, by the toolbar, to the single sign-on site, the non-single sign-on site, the system, the mainframe, the mainframe or user device application based on the one or more user credentials.
US09542548B2
A method of providing restricted access to computer application information via a computing device includes: displaying a limited-access icon on a display of the computing device, the limited-access icon including a function indicator and code-entry segments that can be selected by a user of the computing device, each of the code-entry segments including a visual indicator; receiving a selection sequence of user selections of selected ones of the code-entry segments; and performing a limited-access function corresponding to the function indicator in response to the selection sequence corresponding to an authorized sequence.
US09542541B1
Recording, analyzing and categorizing of user interface input via touchpad, touch screens or any device that can synthesize gestures from touch and pressure into input events. Such as, but not limited to, smart phones, touch pads and tablets. Humans may generate the input. The analysis of data may include statistical profiling of individual users as well as groups of users, the profiles can be stored in, but not limited to data containers such as files, secure storage, smart cards, databases, off device, in the cloud etc. A profile may be built from user/users behavior categorized into quantified types of behavior and/or gestures. The profile might be stored anonymized. The analysis may take place in real time or as post processing. Profiles can be compared against each other by all the types of quantified behaviors or by a select few.
US09542531B2
A modular system for acquiring biometric data includes a plurality of data acquisition modules configured to sample biometric data from at least one respective input channel at a data acquisition rate. A representation of the sampled biometric data is stored in memory of each of the plurality of data acquisition modules. A central control system is in communication with each of the plurality of data acquisition modules through a bus. The central control system is configured to control communication of data, via the bus, with each of the plurality of data acquisition modules.
US09542528B2
Automated, standardized and accurate extraction of relationships within text. Automatic extraction of such relationships/information allows the information to be stored in structured form so that it can be easily and accurately retrieved when needed. Such information can be used to build online search engines for highly specific and accurate information retrieval. Generally, according to the current invention, extracting such information (i.e., relationships within text) from raw text can be accomplished using natural language processing (NLP) and graph theoretic algorithm. Examples of such textual relationships include, but are not limited to, biological relationships between biological terms such as proteins, genes, pathways, diseases and drugs. The current methodology is also able to recognize negative dependences in context, match patterns, and provide a shortest path between related words.
US09542524B2
Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.
US09542522B2
Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
US09542519B2
A computer sets a first timing condition for plural registers included in first design information of a semiconductor integrated circuit, and executes first logic synthesis to generate second design information. The computer sets, for the registers, a second timing condition having a smaller timing margin than the first timing condition, and executes second logic synthesis to generate third design information. The computer calculates an area change rate caused by a difference between the timing conditions, on the basis of the second and third design information with respect to each logic cone including a register at its end point, and categorizes the registers into a first group and a second group having smaller change rates than the first group, according to the change rate. The computer executes third logic synthesis with the second timing condition set for the first group and the first timing condition set for the second group.
US09542490B2
A video processing device includes a content analyzer that receives a video signal and generates content recognition data based on the video signal, wherein the content recognition data is associated with at least one timestamp included in the video signal. A metadata search device generates time-coded metadata in response to content recognition data and in accordance with the at least one time stamp. A metadata association device generates a processed video signal from the video signal, wherein the processed video signal includes the time-coded metadata.
US09542476B1
Methods, systems, and apparatus, including computer program products, for refining search queries. In one implementation, a method includes obtaining a submitted search query, and in response to obtaining the search query: obtaining search results responsive to the search query; selecting a document from a group of documents identified by the search results; generating from a subset of one or more entities associated with the document one or more candidates for refined search queries, including: identifying one or more terms in the search query, where the one or more terms occur in the search query in a particular order relative to each other, and combining the one or more terms with the entity to generate a candidate, where the one or more terms occur in the particular order relative to each other; and identifying one or more of the candidates as being refined search queries for providing with the search results.
US09542471B2
A method of building a geo-tree includes collecting a plurality of data items having geographic and contextual tags, associating the geographic tags with the contextual tags, clustering the collected data items based on the contextual tags, classifying the clusters based on the contextual tags, building a geo-tree with each classified cluster being associated with a node on the tree and storing the geo-tree.
US09542469B2
In the context of data administration in enterprises, an effective manner of providing a central data warehouse, particularly via employing a tool that helps by analyzing existing data and reports from different business units. In accordance with at least one embodiment of the invention, such a tool analyzes the data model of an enterprise and proposes alternatives for building a new data warehouse. The tool, in accordance with at least one embodiment of the invention, models the problem of identifying fact/dimension attributes of a warehouse model as a graph cut on a Dependency Analysis Graph (DAG). The DAG is built using existing data models and the report generation scripts. The tool also uses the DAG for generation of ETL (Extract, Transform Load) scripts that can be used to populate the newly proposed data warehouse from data present in the existing schemas.
US09542468B2
Data synchronization requires much time if synchronization is started from an initial state where synchronization between databases is not performed, and when a synchronized record is updated during the synchronization process, synchronization of records must be performed again, so that the amount of communication for synchronization is increased. Therefore, when starting synchronization, data synchronization is performed based on a method using a table indicating the synchronization statuses between databases, and at the final stage of synchronization, data synchronization is performed based on a query transmission method using update logs. The remaining synchronization time is periodically calculated of a case where synchronization is continued via the table method and a case where synchronization is performed by switching to the query transmission method, and the synchronization method is switched if the calculated remaining synchronization time becomes shorter when switched to the query transmission method.
US09542465B2
Systems and methods that restore a failed reconfiguration of nodes in a distributed environment. By analyzing reports from read/write quorums of nodes associated with a configuration, automatic recovery for data partitions can be facilitated. Moreover, a configuration manager component tracks current configurations for replication units and determines whether a reconfiguration is required (e.g., due to node failures, node recovery, replica additions/deletions, replica moves, or replica role changes, and the like.) Reconfigurations of data activated as being replicated from an old configuration to being replicated on a new configuration may be performed in a transactionally consistent manner based on dynamic quorums associated with the new configuration and the old configuration.
US09542445B2
The invention relates to a computer system and a corresponding method and a corresponding computer-readable medium. The computer system is suitable for determining the result of a join. Based on the access pattern of an application, the computer system infers that a particular subjoin is empty. The computer system then excludes the inferred-empty subjoin when performing the join, performing a more efficient and faster database join operation.
US09542443B2
Techniques for processing a query are provided. One or more operations that are required to process a query are performed by a coprocessor that is separate from a general purpose microprocessor that executes query processing software. The query processing software receives a query, determines one or more operations that are required to be executed to fully process the query, and issues one or more commands to one or more coprocessors that are programmed to perform one of the operations, such as a table scan operation and/or a lookup operation. The query processing software obtains results from the coprocessor(s) and performs one or more additional operations thereon to generate a final result of the query.
US09542442B2
Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.
US09542441B1
The specification relates to a method of receiving a first query and a second query. The method analyzes the second query for a presence of anaphora. If anaphora is present, the method analyzes the first query for a presence of an entity that can be associated with the anaphora. If the analysis analyzing the first query returns two or more associated entities, the method forms a third query wherein the anaphora of the second query is replaced with one of the associated entities and forms a fourth query wherein the anaphora is replaced with the other of the associated entities. The third query and the fourth query are sent to a query-ranking engine. The third query and the fourth query receive a ranking and the higher-ranked query is sent to a search engine.
US09542438B2
Real-time query expansion (RTQE) is a process of supplementing an original query with additional terms or expansion choices that are ranked according to some figure of merit and presented while users are still formulating their queries. As disclosed herein, individual terms may be combined and submitted as a phrase into a query. By building the phase term-by-term, users can compositionally formulate queries while maintaining the same benefits that other RTQE interfaces offer. To promote greater flexibility in its working environment, the number of terms that are presented on a display may be reduced. In place of some terms, placeholders may be used and expanded by the user when necessary. This allows phrases to be readily presented on small displays (e.g., hand-held devices).
US09542428B2
Disclosed are systems, apparatus, and methods for identifying and processing duplicative records in one or more database systems. In various implementations, a first data object may be created and stored in a first database system, where the first data object includes a plurality of data fields capable of storing a plurality of data values. A trigger function may be executed in response to creating the first data object, where the trigger function causes one or more servers to determine if one or more existing data objects stored in the second database system match the first data object, and where the trigger function further causes one or more servers in the first database system to retrieve one or more data values from the one or more existing data objects. The retrieved one or more data values may be stored in one or more data fields of the first data object.
US09542421B2
Systems and methods for sequencing electronic files include generating a first file sequence and one or more alternative file sequences. An alternative file sequence may be generated based in part on a characteristic of a file in the first sequence. The first and alternative sequences may be used in an electronic slideshow that allows a user to switch between file sequences. In some implementations, which alternative file sequences are generated may be determined based in part on a prediction of characteristics that may be of interest to a user.
US09542420B2
Functionality is described for data management and querying LC/MS spectrometry data, therefore making it easier to store, retrieve, transfer, and process the mass spectrometry data. The functionality transforms a plurality of raw LC/MS files obtained from a biological experiment into a set of LC/MS images on a common M/Z and RT grid compatible for image processing (e.g., time alignment, peak detection and quantification, differential analysis, etc.). The functionality then spits large LC/MS images into smaller chunks, therefore making easier parallel querying and processing using cloud or high performance computing systems.
US09542411B2
For adding cooperative file coloring in a similarity based deduplication system using a processor device in a computing environment. Input streams of backup application are parsed and the data segments are marked with file coloring that represents a source file of the backup application for comparing the data segments to determine if the data segments are identical during a similarity check operation.
US09542400B2
Embodiments of the present invention are directed to systems and methods for providing archival support for one or more services provided by a cloud infrastructure system. One such method comprises receiving a message corresponding to an archive trigger event, and determining based on the message one or more services subscribed to by a customer of a cloud infrastructure system which are to be archived. The method further comprises sending an instruction to the one or more services to archive customer information, and storing each archive in an archive directory accessible to the customer.
US09542393B2
A method and system for indexing, searching, and retrieving information from timed media files based upon relevance intervals. The method and system for indexing, searching, and retrieving this information is based upon relevance intervals so that a portion of a timed media file is returned, which is selected specifically to be relevant to the given information representations, thereby eliminating the need for a manual determination of the relevance and avoiding missing relevant portions. The timed media includes streaming audio, streaming video, timed HTML, animations such as vector-based graphics, slide shows, other timed media, and combinations thereof.
US09542376B2
Systems and processes are described for creating, editing, and navigating one or more flowcharts. A process includes causing display of a graphical user interface having a plurality of display regions. The plurality of display regions including at least a first, a second, and a third display region. Each display region is for displaying a node of a plurality of nodes in the one or more flowcharts. The plurality of nodes are connected by a plurality of logic paths and the total number of display regions is less than the total number of hierarchical levels in the one or more flowcharts. Additionally, the process includes causing display of a first node in the first display region and a second node in the second display region. A first logic path connects from the first node to the second node.
US09542374B1
Aspects of the present disclosure are directed to methods and systems for applying electronic signatures to an electronically stored document wherein the electronic signatures are associated with a specific revision of that electronically stored document (revision specific electronic signatures).
US09542367B2
In response to reception of an electronic data interchange (EDI) instance document, a determination is made that a hierarchical EDI reception processing rule sequence, useable to partition encoded hierarchical envelopes of the EDI instance document and to invoke processing of payload data packaged within the encoded hierarchical envelopes, has not been configured. Through analysis of content of the EDI instance document, an EDI standard and syntax formatting of the encoded hierarchical envelopes that package the payload data within the EDI instance document are determined. An EDI reception processing sequence definition that encodes the hierarchical EDI reception processing rule sequence is configured that is usable to partition the encoded hierarchical envelopes of the EDI instance document and to invoke the processing of the payload data packaged within the encoded hierarchical envelopes.
US09542365B1
A method includes accessing, by a server computer, a plurality of electronic mail messages; identifying, based on information contained in each electronic mail message, one or more actions that can be taken with respect to each electronic mail message; and outputting, for display at a client computing device, an electronic mail interface. The electronic mail interface includes a message preview element for each electronic mail message. Each message preview element includes an interface element for causing performance of the action for each electronic mail message.
US09542363B2
Method and system for processing a page-image based input document such as PDF and generate output documents, in a page-image based format or another format, which have a different layout than the original document. Certain contents in the original document removed and other contents are reorganized in this process. The method is used to re-target documents for different types of display devices, such as desktop and laptop computers, tablet computers, e-readers, smart phones, etc. When generating the output documents, the method takes into consideration the different form factors of the display devices as well as the different types of user input devices and methods such as touch screen (including different gestures used, whether stylus or finger is used for input, etc.), physical keyboard, mouse, etc. used by the targeted display device, so that each output documents is optimized for a particular type of display device.
US09542361B2
A system and method may truncate entered text of a text box user interface element to display both a beginning portion of the text and an ending portion of the text. Within a displayed user interface, a collapsible text entry box may include a text entry field having a maximum size based on a spatial relationship between the field and the box. The text entry field may include a text entry capacity of a threshold number of characters based on the text entry field parameter. The field may receive a stream of characters and the user interface may initially display all characters as the field receives them. When the displayed characters exceeds the threshold number, the system and method may truncate the displayed characters at a truncation point. The position of the truncation point may include a displayed character after a first displayed character of the received character stream.
US09542360B2
Systems and methods are disclosed to analyze a patent document by identifying at least one element and relationship to other element(s) in a figure; analyzing text description of the element and relationship to other element(s); generating a user manipulable claim data structure including elements in a potential claim; and displaying a relationship between claims and showing the claims as one or more text nodes.
US09542358B1
An electromagnetic interference (EMI) signal is processed by digitizing the EMI signal, generating a plurality of overlapping time records from the digitized EMI signal, applying a window function to the plurality of overlapping time records to produce a plurality of modified time records, wherein the window function has a substantially flat top, and performing a fast Fourier transform (FFT) on each of the modified time records to produce a plurality of corresponding amplitude envelopes.
US09542349B2
Methods and structure for emulating wide ports at an expander are provided. An exemplary system includes a Serial Attached Small Computer System Interface (SAS) expander. The expander includes a plurality of physical links, and a controller. The controller is able to identify a physical link coupled with a device, to generate a plurality of virtual physical links that are configured as a virtual wide port coupled with the device, and to present the virtual wide port at the expander in place of the physical link.
US09542340B2
An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI.
US09542337B2
Described is a technology by which a transient storage device or secure execution environment-based (e.g., including an embedded processor) device validates a host computer system. The device compares hashes of host system data against valid hashes maintained in protected storage of the device. The host data may be a file, data block, and/or memory contents. The device takes action when the host system data does not match the information in protected storage, such as to log information about the mismatch and/or provide an indication of validation failure, e.g., via an LED and/or display screen output. Further, the comparison may be part of a boot process validation, and the action may prevent the boot process from continuing, or replace an invalid file. Alternatively, the validation may take place at anytime.
US09542333B2
Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining whether a number of available physical pages on the first and second local volatile memory devices exceeds a minimum threshold for initiating replication of memory data between the first and second local volatile memory devices; and if the minimum threshold is exceeded, allocating a first physical address on the first local volatile memory device and a second physical address on the second local volatile memory device to a single virtual page address.
US09542330B2
Storage tracks from at least one host are destaged from the write cache rank when it is determined that the at least one host is idle with respect to a first set of ranks, and storage tracks are refrained from being destaged from each rank when it is determined that the at least one host is not idle with respect to a second set of ranks.
US09542328B2
Methods, computing systems and computer program products implement embodiments of the present invention that include initializing, by a processor executing a file system in communication with a block manager managing multiple storage regions on a storage device, a file system write cache to have a default cache size, the default cache size corresponding to a first storage capacity of a default number of the storage regions. Upon detecting that a current number of the storage regions that are not in use by the block manager is less than the default number, the file system write cache is resized to a reduced cache size that corresponds to a second storage capacity of the current number of the storage regions. While the file system write cache has the reduced cache size, the file system write cache can be resized back to the default cache size as unused storage regions become available.
US09542323B2
A computing system includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction in an out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.
US09542320B2
Systems and methods maintain cache coherency between storage controllers using input/output virtualization. In one embodiment, a primary storage controller receives write commands over a virtualized interface, stores the write commands in cache memory, tracks a status of the write commands processed from the cache memory, and stores the status in a portion of the cache memory. A backup storage controller includes a backup cache that receives replications of the write commands via direct memory access operations, and stores the replications of the write commands. The primary storage controller makes the status available to a host system. In response to a failure of the primary storage controller, the backup storage synchronizes with the status from the host system, and resumes I/O operations for the logical volume.
US09542315B2
A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array.
US09542312B2
Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.
US09542311B2
The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory. By skipping some logic pages, the present invention effectively reduces the floating gate coupling effect in the horizontal, diagonal and vertical directions of the multi-layer storage flash memory in the programming process. Therefore, the error rate is reduced, the service life of the device is prolonged, and the reliability of the whole system is enhanced.
US09542303B2
System and method for reversibility categories and characteristics of computer application functions
Disclosed embodiments provide a system, machine-readable medium, and a method that may test computer application functions. A system provides for testing a computer application function by analyzing a testing characteristic of the computer application function information. Based on the analysis of the testing characteristic, the computer application function may be activated for testing in any one of a plurality of test environments. The test environment is selected according to the testing characteristic that indicates the effects that the testing of the selected computer application has on the test environment. This allows users to select a test environment based on the effects that it has on a test system.
US09542302B2
A system includes an intervening server, an information processing apparatus, and an image forming apparatus. The information processing apparatus i) sends debug command information including a debug command and a first identifier to the intervening server, ii) periodically requests for operation log information including an operation log and a second identifier to the intervening server, iii) receives the operation log information, and iv) stores the operation log associated with the debug command, if the first identifier matches with the second identifier. The image forming apparatus i) periodically requests for the debug command information to the intervening server, ii) receives the debug command information, iii) acquires the operation log of an application in response to the debug command, and iv) sends, to the intervening server, the operation log information including the operation log and the second identifier included in the debug command information.
US09542301B1
More robust testing of computer module responses to processing errors using a flexible, lightweight solution that does not alter the computer module. Through modification of processing pointers, a wide variety of processing errors and delays are injected into a computer module without modifying the computer module.
US09542296B1
In a provider network, attributes of one of a plurality of storage devices of the provider network are identified for failure monitoring. Based on a failure prediction model, a predicted probability of failure of the selected storage device is determined. The failure prediction model is based on historical and current data associated with failures of the storage devices of the provider network that have common attributes. The selected storage device is deactivated in response to determining that the predicted probability of failure of the selected storage device meets a criterion.
US09542293B2
Methods and systems for collecting and processing quality of service (QOS) data are provided. A collection module receives the QOS data from a storage operating system for a plurality of storage volumes at time t2, when a process for collecting the QOS data began at time t1 such that t2>t1. The collection module estimates a QOS data value for time t1 and provides the estimated QOS data value to a performance manager that uses the estimated QOS data value for monitoring QOS for the plurality of storage volumes using a plurality of resources for processing input/output (I/O) requests.
US09542286B2
A memory system logs failures to optimize garbage collection in partial bad blocks that are reused in non-volatile memory. A failure in a primary block may be logged in an inverse global address table. A garbage collection operation can reference the log in order to automatically avoid the failure in the primary block when the primary block is picked as the source block for garbage collection. Likewise, the garbage collection operation may scan only the logged wordlines in the secondary block when the secondary block is picked as the source block for garbage collection.
US09542285B2
A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.
US09542284B2
A mechanism is provided for direct memory access in a storage device. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism writes to the first memory buffer based on the memory command. Responsive to the buffer being full, the mechanism deterministically maps addresses from the first memory buffer to a plurality of solid state drives in the buffered flash memory module using a modular mask based on a stripe size. The mechanism builds a plurality of input/output commands to persist contents of the first memory buffer to the plurality of solid state drives according to the deterministic mapping and writes the contents of the first memory buffer to the plurality of solid state drives in the buffered flash memory module according to the plurality of input/output commands.
US09542281B2
Systems and methods herein obtain snapshots of one or more applications, while having minimal impact on performance of the applications. Embodiments may involve obtaining snapshots of modified application data within a node without disturbing the operations of the application. Systems may be configured to leverage the fast characteristics of local storage devices while utilizing the advantages provided by the remote storage of data. One or more applications may be preconfigured to record data modifications in one or more associated application state storages located on local memory. Further, one or more systems may operate in the background to identify modifications made to the associated application state storages and to determine an appropriate moment to take one or more snapshots of the stored data and transfer the one or more snapshots to one or more remote locations to be stored. Several factors may be used to determine when an appropriate moment has occurred.
US09542275B2
Embodiments in accordance with the present invention disclose a method, computer program product, and system for optimizing performance of a computer backup solution that includes at least two data movers. The automated method includes measuring data mover performance during operation of a backup cycle, and optimizing the performance of data movers by increasing or decreasing the number of threads operating concurrently in the data movers. The method further includes computation of performance rankings of the data movers and shifting workload among the data movers in accordance with their respective performance rankings, such that the computer backup solution converges toward an optimized configuration.
US09542274B2
A method of managing content in a network by a cache repository that includes receiving content from a content source; storing the content in the cache repository; sending the content to a remote repository for storage; and determining if a connection to the remote repository can be established in the network. If the connection to the remote repository can be established, the method includes retrieving the content from the remote repository; and if the connection to the remote repository cannot be established, the method retrieves the content from a backup repository.
US09542268B2
A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.
US09542267B2
Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.
US09542265B2
A method for decoding a headerized sub data set (SDS) according to one embodiment includes decoding a header from a headerized SDS to obtain a SDS. C1 and C2 decoding are performed on the SDS in a number of iterations based on a number of interleaves in each row of the SDS. A number of columns of the SDS are overwritten with successfully decoded C2 codewords. A number of rows of the SDS are overwritten with successfully decoded C1 codewords. A number of C1 and/or C2 codewords of the SDS are erased. Remaining rows and/or columns of the SDS are maintained as uncorrected. The SDS is output when all rows of the SDS include only C1 codewords and all columns of the SDS include only C2 codewords.
US09542262B1
A method for error correction, the method comprises receiving a codeword that comprises a payload and a redundancy section; error-correction decoding the codeword by applying a syndrome-based error correction process to provide an amended payload and an error-correction decoding success indicator; wherein the amended payload comprises an amended CRC signature and an amended payload data; calculating, using the amended payload CRC signature, a validity of the amended payload to provide a CRC validity result; estimating a number of errors in the redundancy section; and determining that the error-correction succeeded when the number of errors in the redundancy section did not exceed a threshold, the error correction success indicator indicates that the error-correction decoding failed, and the CRC validity result indicates that the amended payload is valid.
US09542259B1
Methods, systems and computer program products for automated resolution of computer system incidents are provided.
US09542250B2
A distributed maintenance mode system and method includes receiving an indicator that a monitored system has entered maintenance mode. Trap data is received for the monitored system. It is determined whether the monitored system is in maintenance mode based on the indicator. The trap data is stored and a billable incident ticket is generated for the monitored system if it is determined that the monitored system is not in maintenance mode. The trap data is stored and no billable incident ticket is generated for the monitored system if it is determined that the monitored system is in maintenance mode.
US09542244B2
A primitives library facilitates compiling, linking, and execution of programs that use specialized processors to perform primitive tasks. Data associated with a primitive may be accessed by a specialized-processor-based storage node manager independently of any other processing device.
US09542242B2
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the communications subsystem being configured to be coupled to an antenna. An applications subsystem includes a software applications module and an abstraction module. The software applications module is to execute an operating system and user applications; the abstraction module is to provide an interface with the software applications module. A controller interface module is coupled to the abstraction module and the interface module and is to convert signals from the applications subsystem into signals that are executable by the communications subsystem. Additional apparatuses and methods are described.
US09542235B2
In one embodiment, a non-transitory processor-readable medium stores code representing instructions that when executed cause a processor to obtain a first mutual exclusion object. The first mutual exclusion object can be a write mutual exclusion object associated with a shared resource. The code can further represent instructions that when executed cause the processor to obtain a second mutual exclusion object associated with an object manager module and define a read event object with a name conforming to a predetermined format. The code can further represent instructions that when executed cause the processor to release the second mutual exclusion object, release the first mutual exclusion object, read at least a portion of the shared resource, obtain the second mutual exclusion object, destroy the read event object and release the second mutual exclusion object.
US09542228B2
To accomplish this, an image processing apparatus, in response to a start-up request for an application, reads a class file of a class of the application, adds, at the beginning of a method included in the read class file, code for recording application information indicating the application to a thread, and loads the class. Furthermore, the image processing apparatus, during execution of the method included in the read class file, allocates memory or a file size to be used for an object to be generated and records application information recorded in the thread to the allocated memory or file size, together with generating the object and managing application information of the generated object, in association with memory size or disk usage.
US09542222B2
A system and method can deploy and manage software services in virtualized and non-virtualized environments. The system provides an enterprise application virtualization solution that allows for centralized governance and control over software and Java applications. The system includes a plurality of resource broker agents. Each resource broker agent resides on one of the plurality of virtualized and non-virtualized machines in the computing environment and can be used to manage the software processes and compute resources running in the computing environment. Each resource broker agent is responsible for starting a set of Virtual Machines running on a specific compute resource and performing resource metering control. The system also includes a virtual machine pool that communicates with the plurality of resource broker agents to create and manage the set of virtual machines for each resource broker agent and collect data.
US09542221B2
Multi-core computers may implement a resource management layer between the operating system and resource-management-enabled parallel runtime systems. The resource management components and runtime systems may collectively implement dynamic co-scheduling of hardware contexts when executing multiple parallel applications, using a spatial scheduling policy that grants high priority to one application per hardware context and a temporal scheduling policy for re-allocating unused hardware contexts. The runtime systems may receive resources on a varying number of hardware contexts as demands of the applications change over time, and the resource management components may co-ordinate to leave one runnable software thread for each hardware context. Periodic check-in operations may be used to determine (at times convenient to the applications) when hardware contexts should be re-allocated. Over-subscription of worker threads may reduce load imbalances between applications. A co-ordination table may store per-hardware-context information about resource demands and allocations.
US09542218B2
A method, system and computer program product for selecting a target hypervisor to run a migrated virtual machine. An “effective priority value,” representing the virtual machine's priority with respect to the other virtual machines running on the same hypervisor, is calculated for the virtual machine when it is running on the source hypervisor as well as if it were to run on a target hypervisor for each possible target hypervisor. The target hypervisor associated with the minimum difference in absolute value terms between the virtual machine's effective priority value calculated when it is running on the source hypervisor and its effective priority value calculated if it were to be migrated to run on a target hypervisor is selected to receive the migrating virtual machine. In this manner, the effective priority metric has enabled a target hypervisor to be chosen that most closely matches the priority environment of the source hypervisor.
US09542210B2
Aspects of an application program's execution which might be subject to non-determinism are performed in a deterministic manner while the application program's execution is being recorded in a virtual machine environment so that the application program's behavior, when played back in that virtual machine environment, will duplicate the behavior that the application program exhibited when originally executed and recorded. Techniques disclosed herein take advantage of the recognition that only minimal data needs to be recorded in relation to the execution of deterministic operations, which actually can be repeated “verbatim” during replay, and that more highly detailed data should be recorded only in relation to non-deterministic operations, so that those non-deterministic operations can be deterministically simulated (rather than attempting to re-execute those operations under circumstances where the outcome of the re-execution might differ) based on the detailed data during replay.
US09542207B2
A computer may comprise a processor and first storage device coupled to the processor. The first storage device contains a basic input/output system (BIOS) executable by the processor. The system may also comprise a second storage device coupled to the processor. The second storage device may contain a management interface usable by an operating system to access the BIOS. A plurality of interface files may also be provided, each interface file being usable by the management interface to access the BIOS and each interface file defining one or methods for use by the interface or BIOS. Upon execution of the BIOS, the processor is to determine a configuration of the system and, based on the determined configuration, to select a particular interface file for use during run-time.
US09542206B2
Embodiments relate to controlling configuration of a computer system comprising one or more exchangeable components. The exchangeable components comprising identification means to store an identifier. A pair of a private key and a public key are generated for each accepted manufacturer of the exchangeable components and a pair of a private key and a public key for the computer system; assigning an identifier for each exchangeable component available for attachment to the system; receiving configuration data comprising a list of encrypted identity records comprising identifiers of the components together with signatures over the data generated with the private key of the respective component manufacturer for each component expected to be attached to the system; and receiving a configuration record. The configuration data of the expected components from the received configuration record is compared with the configuration data of the components attached to the system.
US09542199B2
One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system.
US09542189B2
One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.
US09542184B2
A circuit arrangement utilizes a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to be fetched and executed directly within the execution unit, and often enabling other logic circuits utilized for other, general purpose workloads to either be powered down or freed up to handle other workloads.
US09542182B2
A method for providing for standardization of variable names in an integrated development environment is provided. The method includes scanning a project source code for variable names, where the project source code is managed by a development team in an integrated development environment. The method includes determining that the project source code contains a non-standard variable name, where the distinction between a standard variable name and the non-standard variable name is defined by a set of standards and semantic rules. The method then includes identifying a location of the non-standard variable name in the project source code.
US09542176B2
Systems and methods for predicting a software build error are described herein. In one example, a method includes detecting a plurality of changes in software. The method also includes identifying a plurality of change lists, wherein a change list is identified for each of the plurality of changes in the software. Additionally, the method includes identifying a characteristic for each change list in the plurality of change lists. Furthermore, the method includes calculating a plurality of probabilities based at least in part on the characteristic of each of the plurality of change lists, wherein each of the probabilities indicates the likelihood of one of the plurality of change lists creating the software build error. The method also includes reporting the plurality of probabilities of the software build error.
US09542162B2
Methods, systems, and apparatuses, including computer programs encoded on computer readable media, for generating a plurality of tokens from one or more source files. The one or more source files include source code in a first programming language. The source code includes one or more static conditionals that include a conditional expression and branch code that is operative when the conditional expression is true. Various configurations are possible based upon the conditionals. A first static conditional that includes one or more nested static conditionals within the branch code associated with the first static conditional is determined. Each of the one or more nested static conditionals is hoisted to a beginning of the branch code associated with the first static conditional. Each innermost branch code does not contain a static conditional, and each possible configuration is preserved.
US09542144B2
The present specification provides an managing a document using printer emulation.
US09542142B2
An image forming apparatus includes an inquiry portion, a determination portion, and a discharge destination display portion. The inquiry portion inquires a terminal device as a transmission source of a print job as to whether or not another terminal device exists near a terminal device. The determination portion, when the other terminal device exists, determines whether or not the other terminal device is included in a transmission destination of a print job of a printed matter existing in a discharge destination, based on the present state of a discharge destination. The discharge destination display portion, when the other terminal device is included in the transmission destination of the print job of the printed matter existing in the discharge destination, displays a discharge destination of a printed matter corresponding to the other terminal device, and user identification information of a user who owns the other terminal device.
US09542132B2
A storage information update method, an image forming apparatus, a system for managing the image forming apparatus, and a mobile device are provided. The method is performed by an image forming apparatus to which at least one identification number is assigned, a storage configured to store the identification number of the image forming apparatus, and a terminal device communicable with the storage. The method includes acquiring, by the terminal device, the at least one identification number of the image forming apparatus and transmitting, by the terminal device, the received at least one identification number to the storage.
US09542131B2
A printing apparatus which communicates with a data providing apparatus includes a printing mechanism which executes a printing operation. The printing apparatus receives a number of print copies, and acquires print data from the data providing apparatus by executing a request processing of transmitting to the data providing apparatus a data request of the print data, and a reception processing of receiving the print data from the data providing apparatus. When executing a printing operation of N copies (N is an integer of 2 or larger), the acquiring executes, for each copy, the request processing and the reception processing to acquire the print data from the data providing apparatus while executing the request processing of the print data of M-th copy (M is an integer of 2 or larger and N or smaller) after the reception processing of the print data of (M−1)-th copy is completed.
US09542128B2
A non-transitory recording medium has a program recorded therein that is executable by a computer. The program causes the computer to implement functions of a detection unit configured to detect an event which occurs in an output apparatus in which intervention of a user is required, and a screen displaying unit configured to display a notification screen including information relating to the event, an instruction reception field configured to receive an instruction to cope with the event from the user, and a preview image displaying reception field configured to receive a request for displaying a preview image of the output data from the user. The screen displaying unit is configured to display the preview image of the output data which was being output by the output apparatus when the event occurred, in response to receiving the request for displaying the preview image of the output data from the user.
US09542127B2
A page containing a large number of graphics and therefore having a high process load can be processed in parallel and quickly by dividing an edge extraction process into a plurality of threads. In this case, if the number of cores is eight, the edge extraction process is performed by allocating four cores to one of regions obtained by dividing a page and the remaining four cores to the other region.
US09542125B1
A method is used in managing data relocation in storage systems. Data relocation elapsed time is determined in a storage system. The data relocation elapsed time indicates time taken to relocate data of storage objects in the storage system. Based on the determination, relocation of data is effected in the storage system. Effecting relocation of the data includes adjusting relocation of the data of a set of storage objects. The number of storage objects in the set of storage objects is changed based on the data relocation elapsed time.
US09542122B2
A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.
US09542111B2
A memory system including parent data and clone data is disclosed, where the clone data represents a clone of the parent data. The system determines whether clone data to be accessed is different from corresponding data in the parent. The system also determines a physical location of the data to be accessed based on whether the data to be accessed is different from the corresponding parent data. The system also accesses the data based on the physical location.
US09542108B2
A system, method, and computer program product are provided for performing fast migration of a virtual resource from one node to another node. The method includes the steps of receiving a first request to migrate a resource from a first node to a second node, transmitting a second request to the second node to create a new instance of the resource, collecting a set of changes associated with the resource in a data structure, and transmitting the data structure that includes the set of changes to the second node. The second node generates the new instance of the resource based on a snapshot of the resource captured by the first node at a previous point in time and updates the new instance of the resource based on the set of changes such that the new instance of the resource on the second node matches the resource on the first node.
US09542103B2
Methods and systems for monitoring quality of service (QOS) data for a plurality of storage volumes are provided. QOS data is collected for the plurality of storage volumes and includes a response time in which each of the plurality of storage volumes respond to an input/output (I/O) request. The process determines an average of N collected QOS data points at any given time; and iteratively analyzes each QOS data point to detect if a step-up or a step-down function has occurred, where a step-up function represents an unpredictable increase in value of a data point and a step-down function is an unpredictable decrease in value of the data point. A subset of the N QOS data points based on when the step-up function or step-down function occurs is selected for analysis and an expected range for future QOS data based on the subset of the N QOS data points is generated.
US09542087B2
An information processing device is provided that includes a display portion, a user recognition portion, a button selection portion, and a display control portion. The display portion displays at least one function button that is related to a function that the information processing device is capable of performing. The user recognition portion recognizes a user who is operating the information processing device. The button selection portion selects, from among the at least one function button that is displayed on the display portion, at least one function button that corresponds to the user who has been recognized by the user recognition portion. The display control portion moves the function button that has been selected by the button selection portion from an initial position on a display screen of the display portion such that the function button is close to a specified position on the display screen.
US09542086B2
An information processing apparatus, which issues a print instruction when a dragged file is dropped on a print object, the apparatus comprises: a layout unit configured to lay out the print object at a first position; and a display control unit configured to display, when the file is dragged, the print object at a second position which is closer to the dragged file than the first position by moving the print object from the first position.
US09542083B2
Various features described herein may include updating settings on a device in response to a themed cover being placed on a device (e.g., a remote control) associated with the device. The settings may be updated to correspond to a theme of the themed cover. Alternatively or additionally, the device may receive access to different content based on the theme. For example, a device may receive filtered content in response to a child-themed cover. In another example, the device may receive additional football-related content in response to a football-themed cover. The device may revert to its original settings and content access in response to the remote control being removed from the themed cover. In some embodiments, a device may update settings or content access in response to other themed devices (e.g., wearable devices) being within a threshold distance of the device.
US09542082B1
A method of matching medical images according to user-defined matches rules. In one embodiment, the matched medical images are displayed according user-defined display rules such that the matched medical images may be visually compared in manner that is suitable to the viewer's viewing preferences.
US09542069B2
A method of creating three-dimensional products customized with user-selected images is described. The method includes storing definitions of products comprising components, receiving indication of selection by a user of a product, receiving indication of selection by a user of at least one image for printing on the product, receiving information regarding placement of the selected image on components of the product, preparing a two-dimensional representation of the components of the product with the image arranged thereon, and causing the printing of the two-dimensional representation on a material.
US09542062B2
A device virtualization service (DVS) is provided that uses a generalized thick client resident on a mobile device to provide user interface generation support to a myriad of services providing mobile device content. The DVS abstracts device specifics from services to provide device independent user experiences to be described by the service and then rendered on the device.
US09542059B2
Automation systems, methods, and mediums. A method includes identifying a value for a data point associated with a device in a building. The value is received from a management system operably connected to the device. The method includes mapping the value for the data point to a graphical representation of the value for the data point. The method includes generating a display comprising a graphic for the building and a symbol representing the device. The method includes displaying the graphical representation of the value for the data point in association with the symbol representing the device. Additionally, the method includes modifying the graphical representation of the value based on a change in the value in response to identifying the change in the value from the management system.
US09542045B2
A method for touch detection performed by a touch processor in an optical touch detection system is provided that includes receiving an image of an illuminated surface included in the optical touch detection system, wherein the image is captured by a camera included in the optical touch detection system, subtracting a background model from the image to generate a mean-subtracted image, identifying a set of candidate touch locations in the mean-subtracted image, classifying the candidate touch locations in the set of candidate touch locations to generate a set of validated candidate touch locations, and outputting a set of final touch locations determined from the set of validated candidate touch locations.
US09542042B2
A method performs a scan operation for a single-layer sensor array that includes transmit (TX) electrodes and receive (RX) electrodes. The method includes determining whether to include a signal value for an RX electrode in a computation of a slope parameter value for a TX electrode. The method computes an index sum based on an index of the RX electrode when the signal value for the RX electrode is included in the computation of the slope parameter value for the TX electrode. The method computes a signal sum based on the signal value for the RX electrode when the signal value for the RX electrode is included in the computation of the slope parameter value for the TX electrode. The method then computes the slope parameter value for the TX electrode based on the signal sum and the index sum.
US09542033B2
Described is an interactive control device (1) for at least one service apparatus (2), comprising a control unit (3), a screen (4) operatively connected to the control unit (3) having touch selection means (5) for interacting with the user. The touch selection means (5) are configurable between an active condition wherein they receive the touch information of the user and an inactive condition wherein they do not receive the touch information of the user. More specifically, the interactive control device (1) comprises a presence and distance sensor (7) operatively connected to the control unit (3) and configured for generating a detection signal (8) representing the presence and the distance of a user relative to the sensor (7). The control unit (3) is configured for receiving the detection signal (8), for processing it and for generating a control signal of at least part of the service apparatus (2) as a function of the processing.
US09542028B2
An optically transparent force sensor that may compensate for environmental effects, including, for example, variations in temperature of the device or the surroundings. In some examples, two force-sensitive layers are separated by a compliant layer. The relative electrical response of the two force-sensitive layers may be used to compute an estimate of the force of a touch that reduces the effect of variations in temperature. In some examples, piezoelectric films having anisotropic strain properties are used to reduce the effects of temperature.
US09542011B2
An immersive virtual reality system for larger, theater-sized audiences is disclosed. The system enables multiple users to collaborate or work together as a group, or enable groups to compete. Users interact with the virtual reality system through the manipulation of handheld interactive devices. Each device has multiple lights forming a pattern. Tracking sensors monitor the handheld devices, and the system interprets the motions of the users and dynamically changes the virtual reality environment based on the motions of the users. The system may assign unique roles for users within a group.
US09541997B2
A three-dimensional user interface apparatus includes a calculation unit that calculates three-dimensional position information on a three-dimensional coordinate space regarding a specific part of a target person by using three-dimensional information acquired from a three-dimensional sensor, a generation unit that generates virtual three-dimensional object data indicating a virtual three-dimensional object disposed in the three-dimensional coordinate space, a state acquisition unit that acquires state information of the specific part of the target person, an operation specifying unit that specifies a predetermined process to be performed from among a plurality of predetermined processes on the basis of a combination of the state information and a change in the three-dimensional position information, a processing unit that performs the predetermined process specified by the operation specifying unit on the virtual three-dimensional object data, and a display processing unit that displays a virtual three-dimensional object corresponding to the virtual three-dimensional object data on which the predetermined process has been performed, on a display unit.
US09541996B1
Disclosed herein are embodiments of an image-recognition based game. In one aspect, a method involves (1) receiving by a computing device an input to initiate a game application, (2) causing the game application to initiate a game, and (3) during gameplay of the game: (a) causing a graphical display of the computing device to display a silhouette object that includes at least a shape of the silhouette object, (b) receiving by the computing device image data of an environment that includes a real-world object, (c) analyzing the image data to determine one or more similarity measures that indicate similarity between the real-world object and the silhouette object, where one of the similarity measures indicates similarity between a shape of the real-world object and the shape of the silhouette object, and (d) causing the graphical display to display a match indication based on the one or more similarity measures.
US09541991B2
An apparatus may include first circuitry coupled to one or more platform components, the first circuitry operative to receive an unfiltered input voltage signal, compare a first voltage level of the unfiltered input voltage signal to a first reference voltage level, and generate a control signal operative to lower operation power of one or more of the one or more platform components when the first voltage level is less than the first reference voltage level.
US09541986B2
A computing device, such as a mobile communication device, is provided that adjusts, based on user interaction with the device, sleep times for a display to enter a sleep mode restricting use of a graphical user interface. The device includes a display providing the graphical user interface and a processor. The processor is configured to cause the display to enter the sleep mode after a sleep time without receiving any user inputs, increase the sleep time responsive to a user input received within a predetermined period of time after entry of the sleep mode and decrease the sleep time responsive to another user input directing the display to enter the sleep mode before passage of the sleep time. The processor may execute similar processes to adjust a plurality of sleep times associated with different applications and different functions within an application.
US09541977B1
A computer-enabled system, method, and medium is provided to correlate intellectual property analysis, for example, patent claim charts, with respect to the analyzed intellectual property and a target product or other intellectual property. Analysis are stored in a manner that enables searching across multiple analysis, and creating reports over multiple analysis. Units of the analysis are associated with a context, inherited, e.g., from the intellectual property document's assignment to a relative role within the organizational hierarchy; and associated with a context derived from the analysis itself. The analysis and respective documents and/or targets of the analysis can be searched/retrieved/analyzed from the hierarchical analysis, the context analysis, and/or the content of the analysis. This obviates the need to store each analysis as a separate document. The representation of the analysis may be static or dynamic. The target or annotations may be visually represented by an item such as a thumbnail or hyperlink, and the system automatically associates the item with the appropriate application program.
US09541975B2
A semiconductor device includes a voltage measurement unit that measures a voltage of a battery, a current measurement unit that measures charging and discharging currents of the battery, a data processing control unit, and a current detection unit. The voltage measurement unit and the current measurement unit are able to measure the voltage and the discharging current of the battery in case that the current detection unit detects that the discharging current exceeds a predetermined threshold. The data processing control unit estimates an internal resistance of the battery based on a voltage measurement value measured by the voltage measurement unit in accordance with the detection performed by the current detection unit and a current measurement value measured by the current measurement unit in accordance with the detection performed by the current detection unit, and calculates an amount of maximum power capable of being supplied from the battery.
US09541963B2
A thin hinge includes a holding seat, an arc-shaped driven member and a torsional force generation assembly. The holding seat includes a base, a housing space and a linear slide track. The arc-shaped driven member is located in the housing space and includes an operational portion, a curved portion connected to the operational portion and a driving portion extended from the curved portion toward the operational portion to couple with the assembly portion. The torsional force generation assembly includes at least one driving arm connected to the arc-shaped driven member, a slide seat connected to the driving arm and located in the housing space corresponding to the linear slide track, a detent plate located at another side of the linear slide track facing the housing space and corresponding to the slide seat, and at least one torsional spring coupled with the slide seat and the detent plate.
US09541959B1
An electronic device is disclosed that redirects light escaping from a display assembly light source to an illuminable region of the electronic device. In some embodiments, the electronic device includes a light guide panel arranged along a rear surface of the display assembly and configured to receive light escaping from a lateral side of the light source. The light guide panel can then be arranged to transport that light to a position behind the illuminable region and emit it back out in a focused beam having a size about the same as the illuminable region. In some embodiments the illuminable region can be a logo or device identifier.
US09541958B2
A method and apparatus for displaying information on at least two touch screens are provided. The method includes sensing a first touch-drag on a first touch screen; sensing a first touch on a second touch screen; and displaying, on at least one of the first and second touch screens, information corresponding to the first touch-drag on the first touch screen and the touch on the second touch screen, if the touch-drag on the first touch screen and the first touch on the second touch screen are simultaneously sensed.
US09541955B2
A system is provided, in which a mobile computing system in a wristwatch form factor incorporates a computing element, a display element, and a belt or strap-like band. A method is proposed, making use of the strap element as a base for expanding the functionality of the system by providing both a mechanical and a data interface between the base system and the expansion module(s).
US09541953B2
An electronic assembly including a first electronic device and a second electronic device is provided. The first electronic device has a first body and a first terminal set disposed in a recess of the first body. The second electronic device has a second body and a second terminal set disposed on the second body in a protruding manner. The first body and the second body are assembled together only by inserting and locking the second terminal set in the recess. Moreover, the first terminal set and the second terminal set are in contact with each other in the recess, such that the first and the second electronic devices are electrically connected to each other via the first terminal set and the second terminal set.
US09541952B2
A display apparatus includes a display module including a flexible display panel for displaying an image, and a variable member for varying a shape of the flexible display panel. The variable member includes a variable section capable of bending in shape. The variable member also includes a driver for supplying mechanical energy to bend the shape of the variable section, where the flexible display panel is varied in shape by the bending in shape of the variable section.
US09541951B2
This display includes a display panel support member having a rear surface partially constituting a rear housing and a cover member mounted on the display panel support member to partially cover the rear surface thereof. A movement regulating portion regulating movement of the cover member is provided on the rear surface of the display support member.
US09541939B2
A switching current source circuit is provided. A current source drains a bias current from a power supply via a first mirror transistor. A second mirror transistor has a source coupled to the power supply, a gate coupled to the gate of the first mirror transistor, and a drain for providing an output current. A switch is coupled between the gates of the first and second mirror transistors, and has a control terminal for receiving a control signal. A first capacitor is coupled between the gate of the second mirror transistor and the voltage generating unit. A second capacitor is coupled between the gate of the second mirror transistor and a ground. The voltage generating unit selectively provides a first voltage or a second voltage different from the first voltage to the first capacitor according to the control signal.
US09541937B2
An in-vehicle communication system capable of performing power supply control of the system according to the user's preference while simplifying the configuration of a control device for controlling a device based on information to be relayed. A control part of a GW device extracts information required for power supply control of loads from CAN messages received by first to third communication parts, specifies vehicle state based on the extracted information, determines power supply states in which the loads preliminarily stored into a power supply state table are to be, by associating the states with the specified vehicle state, and then transmits control information for providing an instruction of the determined power supply state to the power supply control device. The power supply state table in the storage part is rewritable, and a part of the power supply state table may be updated according to the preference of a vehicle's user.
US09541936B2
A circuit for balancing a voltage across a semiconductor element series-connected with other semiconductor elements of the same type may include a comparator configured to compare data representative of a voltage across the semiconductor element with a reference voltage, and a resistive element of adjustable value and configured to be controlled by the comparator.
US09541930B2
A system for reducing power consumption in a power supply circuit including: a transformer including: a core; a first winding including a first end and a second end of a first wire wound on the core; a second winding including a first end and a second end of a second wire, wherein the second wire has a larger cross-section than the first wire and the second end of the first wire is connected to the first end of the second wire; an input electrically connecting the first and second windings to the power supply circuit; and an output for connecting to a load; and a controller connected to the transformer for controlling an output voltage at the output, wherein the output voltage is less than a supply voltage at the input, to reduce the power consumption of the load.
US09541928B2
A power supply device includes: a comparator that compares an error voltage and a slope voltage to generate a comparison signal; a PWM pulse generation portion that generates a PWM pulse based on a clock signal and the comparison signal; an on-time fixed pulse generation portion that uses the comparison signal as a trigger to generate an on-time fixed pulse where an on-time and an on-time number are constant; a one shot pulse generation portion that generates once, when a soft start voltage exceeds a predetermined threshold voltage, a one shot pulse where the on-time and the on-time number are constant; and a selector that selects any one of the PWM pulse, the on-time fixed pulse and the one shot pulse.
US09541906B2
A controller includes a control unit, at least one DOF (Dynamic Offshoot Factor) unit, and a compensation unit. The control unit produces an output signal for a process according to a measured signal and a reference signal, so that the measured signal can be changed to approach the reference signal. The DOF unit receives a selection signal corresponding to a variable of the process that affects the measured signal or is affected by the control unit. Also, the DOF unit produces a DOF signal according to short-time and long-time average values of the selection signal. The compensation unit incorporates the DOF signal into one of the measured signal, the reference signal, and the output signal to obtain a compensation signal being sent back to the control unit, instead of the measured signal, the reference signal or the output signal, to facilitate controlling the process.
US09541904B2
A method for interacting with a user through a smart watch can include displaying an interactive image. The method can further include detecting a contact moving continuously from a first edge of the touch-sensitive display toward a second, opposite edge of the touch-sensitive display. In response to the detection, the touch-sensitive display can display select function indicators in accordance with movement of the contact. The select function indicators can comprise four or fewer distinct, selectable icons.
US09541894B2
An image forming apparatus (1) includes a main body (10), a recording medium accommodating section (20), a paper feed section (30), an upstream conveyance section (60), an image forming section (40), a downstream conveyance section (70), a reverse conveyance section (P2), a covering member (80), and a movable guide section (90). The downstream conveyance section (70) includes an ejection section (50) and a reversing section (73). The covering member (80) moves between a closed position where the upstream conveyance section (60) is composed and an open position where the upstream conveyance section (60) is exposed. The movable guide section (90) moves between a first position where the downstream conveyance section (70) is composed and a second position where the downstream conveyance section is exposed. The movable guide section (90) moves in conjunction with the covering member (80), is located at the first position to guide a recording medium reversed by the reversing section (73) from a first reverse path (Pr1) to a second reverse path (Pr2) when the covering member (80) is located at the closed position, and is located at the second position when the covering member (80) is located at the open position.
US09541886B2
An image forming apparatus includes an image bearing member having an inorganic protective layer on a surface thereof, a cleaning blade having an inclined surface cut out at a corner portion on a side of the image bearing member, and a support portion that supports the cleaning blade so that the inclined surface is in contact with the image bearing member.
US09541874B2
A fixing device includes a heating unit, an endless belt body that follows rotation of the heating unit, and a pressing unit that faces the heating unit with the endless belt body interposed therebetween. The pressing unit includes a retaining body that rotatably retains the endless belt body, a pressing-area-forming portion that is a part of the retaining body, and a pressing member provided on an upstream side of the retaining body with respect to the pressing-area-forming portion in a direction of rotation of the endless belt body, the pressing member being a metal plate that is bent along a line extending in a longitudinal direction thereof. The pressing unit is movable relative to the heating unit between a position where a pressing area is formed by the pressing-area-forming portion and the pressing member and a position where the pressing area is formed by the pressing member.
US09541859B2
An electrophotographic image forming apparatus may include an imaging cartridge and a toner cartridge that are detachably attached to a main body, a first optical sensor that is mounted in the imaging cartridge and detects a toner level in a development chamber, and a second optical sensor that is mounted in the toner cartridge and detects a toner level in the development chamber.
US09541855B2
A signal processing device that generates an output signal from image data by using a clock corresponding to the pixels of the image data, the signal processing device includes: a delayed signal group generating unit that generates a group of delayed signals with a delay element group formed with stages of delay elements; a clock adjusting unit that generates a modulation/synchronization clock from the group of delayed signals by referring to phase data matching the clock with a predetermined phase and frequency modulation coefficient data converting the clock to a predetermined frequency; and a PWM processing unit that generates a PWM signal from the group of delayed signals by referring to the phase data, the frequency modulation coefficient data, the modulation/synchronization clock, and the image data, the PWM signal having a pulse width corresponding to the value of the image data.
US09541851B2
A low energy consumption monochrome particle includes a core latex having a core a glass transition temperature and a weight average molecular weight. A shell encapsulates the core and includes a shell latex having a shell glass transition temperature and a weight average molecular weight. The glass transition temperature of the shell latex is higher than the glass transition temperature of the core latex. The weight average molecular weight of the shell latex is lower or higher than the weight average molecular weight of the core latex. The low energy consumption monochrome particles are suitable for high speed printing in SCD systems while decreasing minimum fusing temperature, maintaining excellent hot offset and storage, and exhibiting a matte finish.
US09541850B2
A photosensitive layer includes a gallium phthalocyanine crystal and 0.2% by mass or more and 20% by mass or less of an arene compound based on the gallium phthalocyanine crystal, and the arene compound has a halogen atom or a halogen-substituted alkyl group, and a sulfonic acid group or a sulfonic acid salt group, as a substituent.
US09541844B2
A method for calibrating a manufacturing device that manufactures solid parts by projecting images onto a photo-curable substrate includes providing the manufacturing device including a projector and an optical train, positioning an imaging plate at a manufacturing position relative to the manufacturing device, and providing a contrasting image on the imaging plate. The method further includes projecting a test image from the projector through the optical train onto the contrasting image and calibrating the projector and/or the optical train in response to the test image projected onto the contrasting image. The method further includes manufacturing a solid component with the manufacturing device after the calibrating.
US09541842B2
A reflective imaging optical system which forms, on a second plane, an image of a pattern arranged on a first plane and illuminated with light from an illumination optical system includes a plurality of reflecting mirrors including first and second reflecting mirrors by which the light reflected by the first plane is reflected first, second, respectively. An area on the first plane illuminated with the light from the illumination optical system is an illumination objective area, the illumination objective area is positioned on a predetermined side of an optical axis of the reflecting mirrors, and reflection areas of the first and second reflecting mirrors are positioned on the predetermined side of the optical axis of the reflecting mirrors; and the first and second reflecting mirrors are arranged so that an optical path of the light from the illumination optical system is positioned between the first and second reflecting mirrors.
US09541829B2
A photosensitive composition comprises a fluorinated solvent, a photo-acid generator and a copolymer. The copolymer comprises at least three distinct repeating units, including a first repeating unit having a fluorine-containing group, a second repeating unit having an acid-catalyzed cross-linkable group, and a third repeating unit having a sensitizing dye. The composition is useful in the fabrication of electronic devices, especially organic electronic and bioelectronic devices.
US09541828B2
The present invention relates to a printing element having at least one polymer layer which has photoimageable constituents and a chemically functionalized polymer to make the polymer layer either more hydrophobic or hydrophilic. In one embodiment, the printing element comprises two adjacent polymer layers on a substrate in which the photoimaged layer comprises a polymer chemically modified with hydrophobic fluoroalkyl side groups to provide differential wetting with hydrophilic inks.
US09541827B2
It is an object of the present invention to improve the curability of a resin composition and a photosensitive composition suitably employed to form e.g., a surface protecting film and an interlaminar insulating film of e.g., an electronic part, while reducing the internal stress remaining in a substrate when the composition is used to form a cured film on the substrate. The photosensitive composition includes a resin (A) having a phenolic hydroxyl group, a crosslinking agent (B1) having at least two oxazoline groups and a crosslinking agent (B2) having at least two groups represented by —CH2OR (wherein R is a hydrogen atom, an alkyl group having 1 to 10 carbon atoms or an acetyl group) and a photosensitive acid-generating agent (C).
US09541824B1
A method and system for inspecting defects saves scanned raw data as an original image so as to save time for repeated scanning and achieve faster defect inspection and lower false rate by reviewing suspicious defects and other regions of interest in the original image by using the same or different image-processing algorithm with the same or different parameters.
US09541823B2
A photomask blank comprising a transparent substrate and a chromium-containing film deposited thereon is provided. The chromium-containing film comprises at least one CrC compound layer comprising up to 50 at % of Cr, at least 25 at % of O and/or N, and at least 5 at % of C. From the blank, a photomask having a photomask pattern formed on the substrate is produced, the photomask being used in photolithography of forming a resist pattern with a line width of up to 0.1 μm, using exposure light having a wavelength of up to 250 nm.
US09541820B2
A light source unit includes a solid light emitting element that emits light in the blue wavelength range, a luminous light emitting portion on which a luminescent material layer is laid out, the luminescent material layer using the light emitted from the solid light emitting element as excitation light to emit light in a wavelength range of which wavelengths are longer than a wavelength of the excitation light, and a light transmitting portion that transmits the light emitted from the solid light emitting element, and an area of a luminescent material that emits luminous light in the green wavelength range is provided at part of the light transmitting portion.
US09541815B2
A device can comprise an outer frame, a platform, and a motion control mechanism. The motion control mechanism can be adapted to permit movement of the platform in a desired direction with respect to the outer frame and inhibit rotation of the platform with respect to the outer frame. An actuator can be contained at least partially within the motion control mechanism.
US09541813B2
An image display device having improved image retention capability by analyzing the mechanism behind the creation of an unwanted electric field applied to an element after a power supply is turned off, and devising a drive method and so forth for compensating for the same, is provided. Electrophoretic particles contain three types of charged particles, C (cyan), M (magenta), and Y (yellow) that are mutually different in color and threshold voltage for starting electrophoresis. When the threshold voltages of C (cyan), M (magenta) and Y (yellow) are respectively Vth3, Vth2, and Vth3, these satisfy the relationship |Vth3|<|Vth2|<|Vth1|. Further, a voltage application unit applies a voltage (VE) different from a reference potential during the final period of image update period. The voltage (VE) is a compensation voltage that suppresses the movement of charged particles.
US09541812B2
The present invention relates to an electrophoretic particle that includes: a core part including an inorganic particle; a shell layer formed on the core part; and a protective layer formed on the shell layer, a method of producing the electrophoretic particle, and an electrophoretic display device including the electrophoretic particle.
US09541811B2
A thin film transistor array panel includes: a gate line and a data line on a substrate, insulatively crossing each other; a thin film transistor connected to the gate line and to the data line; a first color filter overlapping the thin film transistor; a second color filter overlapping the first color filter; a passivation layer covering the first color filter and the second color filter; a first pixel electrode on the passivation layer, the first pixel electrode overlapping the first color filter and the second color filter; and a second pixel electrode on the first pixel electrode, the second pixel electrode overlapping the first color filter and the second color filter and connected with a drain electrode of the thin film transistor.
US09541808B2
A liquid crystal display device includes a first substrate on which a thin film transistor is formed. The liquid crystal display device includes a first transistor which has a gate electrode thereof formed on a side more remote from the first substrate than a semiconductor layer and has a drain electrode thereof connected to the drain line, a second transistor which is connected to the first transistor in series, and has a source electrode thereof electrically connected to a pixel electrode, and a light blocking layer which is formed between the semiconductor layer and the first substrate and blocks a backlight incident from a first substrate side. The light blocking layer is formed in an overlapping manner on the first transistor, blocks a backlight incident on a first transistor side, and allows a backlight incident on a second transistor side to pass therethrough.
US09541804B2
A liquid crystal display including: a lower electrode; an upper electrode facing the lower electrode; and a liquid crystal layer disposed between the lower electrode and the upper electrode and including a plurality of liquid crystal molecules aligned perpendicular to surfaces of the lower electrode and the upper electrode, wherein the lower electrode includes a center electrode disposed at the center thereof, a first cutout disposed at the center of the center electrode, and a plurality of minute branches disposed extending outwardly from a side edge of the center electrode, and the upper electrode includes a second cutout disposed between the minute branches and the first cutout, a third cutout connected to upper and lower vertices of the second cutout to form a boundary among a plurality of sub-regions together with the first cutout and a fourth cutout connected to left and right vertices of the second cutout.
US09541798B2
A method of manufacturing a liquid crystal display panel is provided, which comprises steps of: manufacturing an array substrate; manufacturing a color film substrate; coating a pixel alignment film on the pixel electrode layer; performing a first optical alignment process on the pixel alignment film; coating a common alignment film on the common electrode layer; performing a second optical alignment process on the common alignment film; and performing an encasing alignment process on the array substrate and the color film substrate. This solves the technological problem of white dropouts on the screen from certain viewing angles.
US09541795B2
A liquid crystal display device including an array of pixels each including first and second substrates, first and second electrodes formed on opposing surfaces of the first and second substrates, which surfaces are positioned opposite to the second and first substrates, first and second alignment restricting portions provided in the first and second electrodes, first and second alignment films covering respectively the first and second electrodes, the first and second alignment restricting portions, and the opposing surfaces of the first and second substrates, and a liquid crystal layer formed between the first and second alignment films and containing liquid crystal molecules, wherein, in each pixel, major axes of a group of liquid crystal molecules are positioned substantially in the same imaginary plane in a predetermined overlapped region between the first and second electrodes, and a pre-tilt is given to the liquid crystal molecules by at least the first alignment film.
US09541794B2
A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The dynamic range of the display may be enhanced by using the second stage to perform local dimming operations. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The color stage and monochromatic stages may share a polarizer. A color filter in the color stage may have an array of red, green, and blue elements or an array of white, red, green, and blue elements. The color stage may be a fringe field display and the monochrome stage may be an in-plane switching display or a twisted nematic stage.
US09541785B2
The conductive sheet according to the present invention includes a base and a conductive portion that is formed on at least one main surface of the base and is formed from a plurality of thin metal wires, where a mesh pattern in which different mesh shapes are arrayed in plan view is formed by the conductive portion, and the mesh pattern is configured such that, in a power spectrum of a two-dimensional distribution of centroid positions of the mesh shapes, an average intensity on a higher spatial frequency band side than a predetermined spatial frequency is larger than an average intensity on a lower spatial frequency band side than the predetermined spatial frequency. The conductive sheet can reduce the granular feeling of noise due to pattern which the conductive sheet has and greatly improve the visibility of an object for observation.
US09541772B2
This invention discloses methods and apparatus for providing a variable optic insert into an ophthalmic lens. A liquid crystal layer may be used to provide a variable optic function and in some examples, an alignment layer for the liquid crystal layer may be patterned in a cycloidally dependent manner. The patterning may allow for a polarization dependent lens in some examples. An energy source is capable of powering the variable optic insert included within the ophthalmic lens. In some examples, an ophthalmic lens is cast-molded from a silicone hydrogel. The various ophthalmic lens entities may include electroactive liquid crystal layers to electrically control optical characteristics.
US09541771B2
Embodiments of this patent disclosure provide for eyeglasses with multiple set of hinges for folding into a compact configuration to be fitted inside a compact case for easy storage and carrying. In one aspect, a pair of foldable eyeglasses having multiple set of hinges is disclosed. The eyeglasses include a frame surrounding a pair of lenses, and a pair of temples each of which extending from an outer edge of the frame, and the eyeglasses are in an unfolded configuration when the eyeglasses is being worn by a user. The eyeglasses also include a horizontal hinge positioned on each temple for folding the pair of temples horizontally from the unfolded configuration toward the frame into a first folded configuration. The eyeglasses additionally include a vertical hinge positioned on each temple for folding the pair of temples vertically from the first folded configuration toward the frame into a second folded configuration.
US09541766B2
Disclosed is a light guiding valve apparatus including an imaging directional backlight, an illuminator array and an observer tracking system arranged to achieve control of an array of illuminators which may provide a directional display to an observer over a wide lateral and longitudinal viewing range, wherein the number of optical windows presented to the observer as viewing windows is controlled dependent on the lateral and longitudinal position or speed of an observer.
US09541757B2
A light flux diameter-expanding element (pupil expanding element) which is used in a retina scanning type display apparatus includes a first diffraction grating having a grating pattern extending in a first direction X, a second diffraction grating, a third diffraction grating, and a fourth diffraction grating, and expands a diameter of the incident light flux in a second direction Y so as to emit the light. In addition, the light flux diameter-expanding element includes a fifth diffraction grating having a grating pattern extending in the second direction Y, a sixth diffraction grating, a seventh diffraction grating, and an eighth diffraction grating, and expands a diameter of the incident light flux in the first direction X so as to emit the light.
US09541745B2
An optical imaging lens includes: a first, second, third, fourth and fifth lens element, the first lens element has an object-side surface with a convex part in a vicinity of the optical axis and a convex part in a vicinity of its periphery; the second lens element has an object-side surface with a convex part in a vicinity of its periphery; the third lens element has positive refractive power, having an object-side surface with a concave part in a vicinity of its periphery; the fourth lens element has positive refractive power, having an object-side surface with a concave part in a vicinity of its periphery and an image-side surface with a convex part in a vicinity of the optical axis; the fifth lens element has an image-side surface with a concave part in a vicinity of the optical axis and a convex part in a vicinity of its periphery.
US09541744B2
An image pickup lens includes an aperture stop, a first lens with positive refractive power having a convex object-side surface, a second lens with negative refractive power having a concave image-side surface, a third lens with positive refractive power having a convex image-side surface, a fourth lens with negative refractive power as a double-sided aspheric lens having a concave object-side surface, and a fifth lens with negative refractive power of a meniscus shape as a double-sided aspheric lens having a concave image-side surface, wherein the fifth lens is designed so that the negative refractive power weakens as the distance from the optical axis increases, and wherein the following conditional expression (1) is satisfied: 0.55
US09541740B2
Aspects relate to a prism array camera having a wide field of view. For example, the prism array camera can use a central refractive prism, for example with multiple surfaces or facets, to split incoming light comprising the target image into multiple portions for capture by the sensors in the array. The prism can have a refractive index of approximately 1.5 or higher, and can be shaped and positioned to reduce chromatic aberration artifacts and increase the FOV of a sensor. In some examples a negative lens can be incorporated into or attached to a camera-facing surface of the prism to further increase the FOV.
US09541738B2
An imaging lens includes a first lens having positive refractive power; a second lens having negative refractive power; a third lens having positive refractive power; a fourth lens having at least one aspheric surface; a fifth lens having at least one aspheric surface; a sixth lens having two aspheric surfaces; and a seventh lens having two aspheric surfaces, arranged in this order from an object side to an image plane side. The first lens is formed in a shape so that both surfaces are convex near an optical axis thereof. The fourth lens is formed in a meniscus shape so that a surface thereof on the object side is concave near the optical axis. The seventh lens is formed in a shape so that a surface thereof on the image plane side is concave near the optical axis.
US09541737B2
Present embodiments provide for a mobile device and an optical imaging lens thereof. The optical imaging lens comprises six lens elements positioned sequentially from an object side to an image side. Through controlling the convex or concave shape of the surfaces of the lens elements and designing parameters satisfying at least one inequality, the optical imaging lens shows better optical characteristics and the total length of the optical imaging lens is shortened.
US09541735B2
A compact low-priced imaging lens which offers a field of view of about 180 degrees and high optical performance. The imaging lens for a solid-state image sensor includes, in order from an object side to an image side, a first lens with negative refractive power having a convex object-side surface and an aspheric image-side surface; a second lens with negative refractive power as a double-sided aspheric lens having a concave surface on the image side; a third lens with positive refractive power; an aperture stop; and a fourth lens with positive refractive power. The first and second lenses are made of plastic material. The imaging lens satisfies conditional expressions (1) and (2) below: −65.0
US09541728B2
A glasses holder including: a clamping unit for securing the glasses; a connection unit connected with the clamping unit and an optical device respectively, so that an eyeglass of the glasses secured by the clamping unit is parallel to an incident surface of optical lens of the optical device. The glasses holder is used for testing of related specs on TV performances, and can improve accuracy of test results.
US09541719B2
A pluggable optical transceiver is disclosed. The optical transceiver provides a pull-tab assembled with a body of the transceiver. The pull-tab comprises a pair of arms and a handle. The arms in an end portion thereof each provides a leg set in a guide formed in the body. Sliding the pull-tab to disengage the optical transceiver from the cage, the leg is slid within the guide to push the end portion of the arm outwardly. The handle provides in an end thereof a bar including a slope. The optical fiber pulled out from the optical connector set in the optical receptacle of the transceiver rides on the slope even when the transceiver is set in the cage by the upside-down arrangement.
US09541718B2
A photoelectric hybrid device includes an optical connector on a flat optical surface at one end of vertical optical waveguides for inputting and outputting an optical signal. Integration of the photoelectric hybrid device into an interposer or the like is standardized. The photoelectric hybrid device includes: conductive pins connected to an electric signal pathway for a photoelectric hybrid substrate; a translucent member having a flat optical surface and a translucent part; and self-organizing optical waveguides that form an optical path between the translucent part and an optical waveguide. The flat optical surface is not lower than the tops of the electrical connection parts on the conductive pins. Collision of the optical connector and the tops of the electrical connection parts can be avoided when an optical connector on which an optical waveguide that transmits an optical signal among the optical waveguides.
US09541714B2
Disclosed are a bidirectional optical transceiver module and a method of aligning the same. The bidirectional optical transceiver module includes: a package having on one side a cavity; a platform mounted on the package; a transmitter which generates output light; a holder which includes the horizontal portion having the through-hole and disposed on the package to cover the cavity, and the vertical portion which has the inclined surface on one side and the connection hole connected to the through-hole; a receiver which generates an electric signal that corresponds to input light incident into the cavity; and a WDM filter that delivers the output light and the input light.
US09541713B2
The present disclosure relates to a fiber optic connector including a connector housing having a distal end and a proximal end. The distal end can form a plug portion adapted for insertion within a receptacle of a fiber optic adapter. A rear insert mounts within the proximal end of the connector housing. An axial insertion/retention interface can be defined between the connector housing and the rear insert. The axial insertion/retention interface can be configured to allow the rear insert to be inserted into and removed from the proximal end of the connector housing along an insertion axis when the rear insert is positioned in a first rotational position about the insertion axis relative to the connector housing. The axial insertion/retention interface can also be configured to prevent the rear insert from being withdrawn from the proximal end of the connector housing along the insertion axis.
US09541701B2
This application describes a back-lit transmissive display including a transmissive display (620) and a variable index light extraction layer (640) optically coupled to a lightguide (630). The variable index light extraction layer has first regions (140) of nanovoided polymeric material and second regions (130) of the nanovoided polymeric material and an additional material. The first and second regions are disposed such that for light being transported at a supercritical angle in the lightguide, the variable index light extraction layer selectively extracts the light in a predetermined way based on the geometric arrangement of the first and second regions. The transmissive display may be a transmissive display panel or a polymeric film such as a graphic.
US09541698B2
A backlight that includes a front reflector (120) and a back reflector (130) that form a hollow light recycling cavity including an output surface (104) is disclosed. At least a portion of the back reflector is non-parallel to the front reflector. The backlight also includes at least one semi-specular element disposed within the hollow light recycling cavity, and one or more light sources (140) disposed to emit light into the hollow light recycling cavity, where the one or more light sources are configured to emit light into the hollow light recycling cavity over a limited angular range.
US09541686B2
A sheet is described. The sheet has at least one substrate and at least one coating, which reflects thermal radiation, on at least one surface of the substrate, wherein the coating on the substrate contains at least one adhesion layer, a functional layer containing at least one transparent, electrically conductive oxide, above the adhesion layer, a dielectric barrier layer, for regulating oxygen diffusion, above the functional layer, and an antireflection layer above the barrier layer, wherein the barrier layer has a thickness from 10 nm to 40 nm.
US09541685B2
A method for producing a reflective optical component for an EUV projection exposure apparatus, the component having a substrate having a base body, and a reflective layer arranged on the substrate, wherein the substrate has an optically operative microstructuring, comprises the following steps: working the microstructuring into the substrate, polishing the substrate after the microstructuring has been worked into the substrate, applying the reflective layer to the substrate. A reflective optical component for an EUV projection exposure apparatus correspondingly has a polished surface between the microstructuring and the reflective layer.
US09541671B2
A calibration site for a gamma-gamma well logging tool for use in mineral exploration, the calibration site having a column consisting of a plurality of blocks of known densities; and a borehole through the column configured to accept the gamma-gamma well logging tool. Further, a method for calibrating a gamma-gamma well logging tool at the calibration site, the method including lowering the gamma-gamma well logging tool into a column consisting of a plurality of blocks of different known densities and having a borehole therein to receive the gamma-gamma well logging tool; raising the gamma-gamma well logging tool at a set rate; capturing a radiation count at a sensor of the gamma-gamma well logging tool; converting the radiation count to a recorded density for a particular depth at a computing device; and comparing the recorded density at each position of the column with the known densities.
US09541658B2
Dynamically allocating different numbers of bits to windows of a series representing a seismic trace
To process seismic data, a set of data values representing a seismic trace is received, and amplitudes of data values associated with plural groups in the set are analyzed. Different numbers of bits are dynamically allocated to at least some of the groups of the set according to the analyzing.
US09541657B2
A bender bar is presented. The bender bar includes at least two pairs of piezoelectric elements arranged on an inert element to adjust the response frequency of the bender bar. In some embodiments, the piezoelectric elements can be stacked on the inert element. In some embodiments, the piezoelectric elements are symmetrically arranged with respect to the bender bar such that a gap is formed between piezoelectric elements arranged on the inert element.
US09541654B2
There is provided an x-ray scintillator (10) including a pore matrix having a plurality of pores formed in a substrate (1). Each of the pores is at least partially covered with a multi-layered coating including at least a reflective layer (2) and a protective layer (3). The at least partially coated pores are filled with scintillating material (4) for absorbing x-ray photons to produce secondary photons, preferably with a wavelength in the visible range. The reflective layer (2) of the multi-layered coating is arranged between the scintillating material (4) and the substrate (1) for reflecting the secondary photons, and the protective layer (3) of the multi-layered coating is arranged between the reflective layer (2) and the scintillating material (4) for protecting the reflective layer while allowing reflection of the secondary photons by the reflective layer.
US09541650B2
A satellite positioning method, a satellite pseudorange calculation apparatus and a satellite pseudorange calculation method thereof are provided. The satellite pseudorange calculation apparatus is used for calculating a pseudorange between a satellite and a satellite positioning receiving device, wherein the pseudorange includes an integer code value and a fractional code value. The satellite pseudorange calculation apparatus comprises a receiver and a processor electrically connected with the receiver. The receiver is configured to receive a code phase from a satellite signal acquisition unit, and the processor is configured to calculate the fractional code value according to the code phase. The receiver is further configured to define an approximation position and calculate the integer code value according to the approximate position and the fractional code value. The satellite positioning method is used for positioning the satellite positioning receiving device.
US09541648B2
In one embodiment, a method comprising, receiving at a moving vehicle first global navigation satellite systems (GNSS) information broadcasted from a base station and second GNSS information provided by one or more satellites; determining by a processor residing in the vehicle a position of the vehicle based on the first and second GNSS information; and re-broadcasting the first GNSS information to a receiver located remotely from the moving vehicle.
US09541647B2
A range finding device includes a transmission module, a linked movement module and a range finding module. The linked movement module is connected to and driven by the transmission module. The transmission module driven by an external driving module enables the linked movement module. The range finding module has one plane which is connected with a plane of the linked movement module and further includes a transmitting portion for transmission of a measurement signal and a receiving portion for reception of the reflected measurement signal, each of which is configured on one side of the range finding module.
US09541645B2
A detecting device is provided. The detecting device detects target objects. The detecting device includes a transmitter configured to transmit transmission waves, a receiver configured to generate reception signals from reflection waves of the transmission waves, a target echo signal detecting module configured to detect target echo signals among the reception signals, a size calculating module configured to calculate a size of each the target objects based on the corresponding target echo signal, and a frequency index value distribution calculating module configured to calculate frequency index values for respective size ranges based on the calculated sizes, each frequency index value being an index of the number of the target objects. The frequency index value distribution calculating module has a first updating submodule configured to update the frequency index value for each size range every predetermined period of time.
US09541642B2
In a method for determining the position and/or the movement of at least one object in the surroundings of a vehicle with the aid of at least one transmitted acoustic signal, the time behavior of at least one electrical signal of an electroacoustic transducer during the transmission of the acoustic signal and/or during a decay of the electroacoustic transducer following the transmission and/or during the reception of the acoustic signal reflected on the object is analyzed at least during a suitable fraction of a signal period in such a way that changes of the electrical signal of the electroacoustic transducer is detected.
US09541634B2
Embodiment of a lightweight and compact wireless precision position tracking device and a precision position tracking motion capture system are described. Optionally, the wireless precision position tracking device is configured to be worn by a user. The wireless precision position tracking device may be configured to emit optical light from two or more respective markers, where the light from one of the markers is distinguishable from light from another of the markers.
US09541632B2
A base station communicates a positioning reference signal (PRS) to wireless communication devices over a downlink in a wireless communication system by encoding a PRS into a first set of transmission resources, encoding other information into a second set of transmission resources, multiplexing the two sets of resources into a subframe such that the first set of resources is multiplexed into at least a portion of a first set of orthogonal frequency division multiplexed (OFDM) symbols based on an identifier associated with the base station and the second set of resources is multiplexed into a second set of OFDM symbols. Upon receiving the subframe, a wireless communication device determines which set of transmission resources contains the PRS based on the identifier associated with the base station that transmitted the subframe and processes the set of resources containing the PRS to estimate timing (e.g., time of arrival) information.
US09541618B2
A state space feedback controller operates in the digital domain for the regulation of the current supply to MRI gradient coils from a multiple-bridge PWM power amplifier. The P1-controller includes an integration part (for the integration of the difference between the demand current and the measured gradient coil current) and a subsequent P-controlled system which in turn includes a delay compensator/stabilizer and a plant. The delay compensator/stabilizer includes a multi-path feedback loop by means of which its digital output signal is fed back through delay blocks, on the one hand, and through filter units, on the other hand. The filter units model the transfer functions of a gradient coil output filter for the gradient coil voltage and the output current of the amplifier inverter units, respectively. In the plant, a filter unit, which models the gradient coil transfer function, is connected in series to a delay chain for the delay of the measurement value of the gradient coil current.
US09541616B2
According to some aspects, a laminate panel is provided. The laminate panel comprises at least one laminate layer including at least one non-conductive layer and at least one conductive layer patterned to form at least a portion of a B0 coil configured to contribute to a B0 field suitable for use in low-field magnetic resonance imaging (MRI).
US09541612B2
A method for measuring a first magnetic field and the temperature of a magneto-resistive transducer includes producing, by the magneto-resistive transducer, a measurement signal dependent on the intensity of the first magnetic field and on the temperature of the magneto-resistive transducer. The method includes establishing a measurement of the intensity of the first magnetic field on the basis of the measurement signal produced and a measurement of the temperature of the magneto-resistive transducer. The method also includes generating a second magnetic field to combine with the first magnetic field to form a resultant magnetic field. The method further includes extracting from the measurement signal, the component which is dependent solely on the second magnetic field and establishing the temperature of the magneto-resistive transducer on the basis of the component extracted.
US09541604B2
A voltage is sensed at a switching device and the voltage is associated with a status of a switching device. The sensed voltage is converted to a useable voltage regardless of the value and type of the sensed voltage. At a single self-contained integrated circuit that is powered by the sensed voltage, the usable voltage is converted into a digital representation. The digital representation is configured to be usable by a processing device to determine the value of the voltage at the switching device.
US09541603B2
A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.
US09541601B2
An embodiment of a testing architecture of integrated circuits on a wafer is described of the type including at least one first circuit of a structure TEG realized in a scribe line providing separation between at least one first and one second integrated circuit. The architecture includes at least one pad shared by a second circuit inside at least one of these first and second integrated circuit and the first circuit, as well as a switching circuitry coupled to the at least one pad and to these first and second circuits.
US09541593B2
A ground fault detection circuit comprising a fuse and a fuse detect circuit. The fuse and the fuse detect circuit are arranged to be coupled in parallel between a reference point and a second point of a monitored circuit for which ground faults are to be detected. The fuse detect circuit is further arranged to detect a fuse break indicative of a ground fault condition and disable at least a portion of the monitored circuit.
US09541592B1
A noise parameter test setup allows accurately measuring the four noise parameters (Fmin, Rn, Γopt) of microwave transistors over a wide frequency range using two wideband directional couplers, instead of SPDT switches, to merge the s-parameter (signal) measurement path and the noise measurement path, avoiding thus the uncertainty of the switching repeatability of the SPDT switches and improving the measurement accuracy. Calibration of the system is the same as when using switches. Additional power control precautions of the VNA sources are necessary to avoid injecting large signal power into the sensitive noise receiver during s-parameter measurements and jamming the weak noise power during noise measurement.
US09541591B2
A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.
US09541587B2
An inverting apparatus and a control method thereof are provided. The inverting apparatus includes an inverting circuit, a detection circuit, and a control circuit. The inverting circuit converts a DC input power into an AC output power. The detection circuit detects an input voltage and an input current. The control circuit provides a control signal for disturbing the input voltage, such that a voltage value of the input voltage is adjusted to a command voltage represented by the control signal. The control circuit calculates an input power corresponding to each of time points, calculates a power variation between the disturbed power and the undisturbed power, then determines whether the power variation is larger than a predetermined variation, and sets a disturbance voltage according to the determination result, based on an MPPT operation or based on a disturbance direction of the command voltage of the previous time point.
US09541586B2
An apparatus for detecting an abnormal event and capturing associated waveforms includes a detection module within a power control device that detects an abnormal condition. The abnormal condition is indicative of an impending failure of the power control device and/or a condition within the power control device indicative of a parameter being outside of a specified limit. The power control device controls power to one or more power devices in a power distribution system. The apparatus includes a signal transmit module that transmits a capture signal to a transient capture meter. The transient capture meter meters transient conditions of a branch of the power distribution system that includes the power control device. The capture signal instructs the transient capture meter to capture current and/or voltage waveforms relevant to a time when the detection module detected the abnormal condition.
US09541584B2
A system may include two input terminals, e.g., HI and LO, and a floating circuit that is physically separate from the input terminals and includes a gain amplifier. The floating circuit can be surrounded by a conductive enclosure that is electrically connected to the second input terminal. The floating circuit can further switch between input signals received from the first and second input terminals to the gain amplifier and the floating circuit ground.
