The invention provides a realizing scheme of a space vector pulse width modulating arithmetic based on FPGA. The scheme divides a space vector pulse width modulating (SVPWM) adjustor into nine modules according to an FPGA modular design philosophy which are: picketage, time-oriented sequential control; sector judging, a state machine, vector selection, time calculation, over modulation, PWM output and dead area adjusting modules. The scheme fully utilizes the parallel processing characteristic of the FPGA as well as the logic realizing and hardware multiplier resources and mainly adopts logical judgment and a plurality of multiplication calculations, thus avoiding the complex calculations like arc tangent and trigonometric function. The scheme supports the modes of over modulation, dead area adjusting, symmetrical PWM and non- symmetrical PWM.