An array substrate for a liquid crystal display device includes: a substrate 100; a gate line 120 on the substrate 100; a data line 130 crossing the gate line 120 to define a pixel region P; a thin film transistor T connected to the gate line 120 and the data line 130, the thin film transistor T including a gate electrode 125 connected to the gate line 120, a semiconductor layer whose boundary is within the gate electrode 125, a source electrode 132 connected to the data line 130 and a drain electrode 134 spaced apart from the source electrode 132; a passivation pattern (158) covering the data line 130 and the thin film transistor; and a pixel electrode 172 extending from the drain electrode 134. The semiconductor layer preferably includes an active layer 140 and an ohmic contact layer 141. A method of manufacturing the array substrate, using a three mask process, is also disclosed.