The invention discloses a double-edge-trigger pipeline accumulator structure of a GaAs heterojunction bipolar transistor (HBT). The structure is a pipeline architecture comprising N stages of 1-bit full adders arranged in parallel, wherein N is a natural number greater than 2, and the 1-bit full adder of each stage outputs the accumulated sum to the external after finishing the accumulation operation and outputs a carry signal to the 1-bit full adder of the next stage. By using the invention, the accumulation operation can be carried out twice within each clock period, thereby realizing that the speed of the accumulator after increasing is actually twice the clock frequency. Thus, the speed of the accumulator is greatly increased.