A memory device includes a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal having the second conductivity type surrounding the channel region. A connector is in contact with the first terminal, and can be connected to a bit line in an overlying patterned conductor layer. Memory material is disposed over the channel region, and can include a dielectric charge storage structure. A control gate surrounds the first terminal and is disposed over the memory material. A conductive line surrounds the control gate and is in contact with the second terminal. The control gate and the conductive line can be ring shaped.