Disclosed is a self-aligned process for providing an improved high-performance bipolar transistor. The transistor device region is isolated from the other devices on the wafer by a wide deep oxide trench (16). The deep oxide trench which has nearly vertical sidewalls, extends from the epitaxial silicon surface through the N * subcollector region into the P-substrate. A shallow oxide trench is used to separate the collector reach through region from the base region. A heavily doped polysilicon layer is used to dope and make contact to the transistor base as well as define the emitter window (28) through which the emitter is doped. In the structure, the separation between the emitter contact and the polysilicon base contact is reduced to a very small value. This is achieved by employing the self-aligned process in accordance with the invention. Metal contact to the polysilicon base contact is done over the deep trench oxide isolation. This allows the transistor base area, and hence the collector base capacitance to be minimized. The shallow emitter and narrow base width of the transistor are formed by ion implantations.