In relatively large systems of (integrated) circuits data signals can experience a delay which is in the order of magnitude of a clock-­pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses (CLK) are led via a delaying element (for example, the inverting circuits in series) (35) to the receiving circuit (slave of the master/slave flip-flop) (22). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/­slave flip-flop) (23), which receives the undelayed clock pulses (CLK), the data delay between the receiving circuit and the other circuit being negli­gible. The data delay is thus in fact distributed over two clock pulses.