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    Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit
    2.
    发明公开
    Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit 失效
    集成电子复用电路和包括这种复用电路的集成电子电路

    公开(公告)号：EP0201128A1

    公开(公告)日：1986-12-17

    申请号：EP86200729.1

    申请日：1986-04-29

    申请人： Philips Electronics N.V.

    发明人： Pfennings, Leonardus Ch. M. G. ,  Veendrick, Hendrikus Josephius Maria ,  Van Zanten, Adrianus Teunis

    IPC分类号： H04J3/04

    摘要： The multiplex circuit inludes a cascade connection of flip-flop elements (118,120,122) for producing a high data-rate multiplexsignal. In order to avoid disturbances caused by parallel loading the flip-flop circuits, the slave-section (130) of the flip-flop generating the multiplexsignal is not parallel loaded, which results in a continuous outputsignal. This way of loading requires a specific flip-flop circuit as shown in the description.

    摘要翻译： 复用电路包括用于产生高数据速率多路复用信号的触发器元件（118,120,122）的级联连接。 为了避免由并行加载触发器电路引起的干扰，产生复用信号的触发器的从属部分（130）不是并行加载的，这导致连续的输出信号。 这种加载方式需要特定的触发器电路，如说明中所示。

    System of circuits with resynchronisation of data
    4.
    发明公开
    System of circuits with resynchronisation of data 失效
    具有数据再同步的电路系统

    公开(公告)号：EP0223275A1

    公开(公告)日：1987-05-27

    申请号：EP86201804.1

    申请日：1986-10-17

    申请人： Philips Electronics N.V.

    发明人： Van Zanten, Adrianus Teunis ,  Veendrick, Hendrikus Josephius Maria ,  Pfennings, Leonardus Chritien Matheus Giellaumus

    IPC分类号： H03K19/003 ,  H03K3/037

    CPC分类号： H03K3/0372 ,  H03K19/00323

    摘要： In relatively large systems of (integrated) circuits data signals can experience a delay which is in the order of magnitude of a clock-­pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses (CLK) are led via a delaying element (for example, the inverting circuits in series) (35) to the receiving circuit (slave of the master/slave flip-flop) (22). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/­slave flip-flop) (23), which receives the undelayed clock pulses (CLK), the data delay between the receiving circuit and the other circuit being negli­gible. The data delay is thus in fact distributed over two clock pulses.

    摘要翻译： 在（集成）电路的相对较大的系统中，数据信号可以经历时钟脉冲周期数量级的延迟。 接收电路（即接收数据信号）然后接收数据信号的时间太晚（时钟脉冲已停止），并且可能在那时不再接管数据信号以用于进一步的处理或传输。 在根据本发明的系统中，时钟脉冲（CLK）经由延迟元件（例如，串联的反相电路）（35）被引导到接收电路（主/从触发器的从机）（22） 。 接收电路的数据输出端连接到接收未延迟时钟脉冲（CLK）的另一电路（另一主/从触发器的主控电路）（23）的数据输入端，接收电路和 其他电路可以忽略不计。 因此数据延迟实际上分布在两个时钟脉冲上。

    Multi-mode memory device
    6.
    发明公开
    Multi-mode memory device 失效
    在mehrere Betriebsarten umschaltbare Speicheranordnung。

    公开(公告)号：EP0295751A1

    公开(公告)日：1988-12-21

    申请号：EP88201219.8

    申请日：1988-06-15

    申请人： Philips Electronics N.V.

    发明人： Van Zanten, Adrianus Teunis ,  Veendrick, Hendrikus Josephius Maria ,  Steenhof, Frits Anthonie ,  Frencken, Peter Hubertus ,  Nillesen, Antonius Hendrikus Hubertus Jozef ,  van der Sanden, Cornelis Gerardus Leonardus Maria

    IPC分类号： G11C19/28

    CPC分类号： G11C19/287 ,  G11C27/04

    摘要： The invention relates to a memory device of the charge-­coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2x2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

    摘要翻译： 本发明涉及电荷耦合移位寄存器类型的存储器件，其被细分为四个部分，每个部分具有例如208,800位的存储容量，并且可以以不同的模式操作：并行/并行输出（ 作为背景视频存储器）; 2x2并行，多路复用/多路复用模式，例如用于100 Hz电视; 扫描模式; 平行再循环模式; “缩短”内存，例如525线系统等。 通过解码和定时块实现控制，其中多位控制字被串行输入和解码。 在扫描模式（例如，作为图文电视存储器）中，存储器部分在单独的扫描寄存器的控制下逐个扫描，其中扫描位（逻辑1）被逐步移位，直到所有部分具有 已阅读 通过数据输出，扫描位例如传送到与前一个存储器件串联连接的另一存储器件（通过其串行数据输入）的扫描寄存器。