A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). Additionally, each peripheral device has a queue control register configured to access a selected channel of the queue memory. The queue memory system described herein efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. The queue memory system will wait for a timing cycle in which the central processing unit does not require use of a bus. At that time, the queue memory system will transfer data between the queue and a peripheral device.