公开(公告)号：EP0668556A3

公开(公告)日：1995-12-06

申请号：EP95301153.3

申请日：1995-02-22

申请人： MOTOROLA, INC.

发明人： Winter, Marlan L. ,  Langan, John A. ,  Sibigtroth, James M.

IPC分类号： G06F13/16 ,  G06F5/06

CPC分类号： G06F5/065 ,  G06F13/1642

摘要： A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). Additionally, each peripheral device has a queue control register configured to access a selected channel of the queue memory. The queue memory system described herein efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. The queue memory system will wait for a timing cycle in which the central processing unit does not require use of a bus. At that time, the queue memory system will transfer data between the queue and a peripheral device.

公开(公告)号：EP0594377A2

公开(公告)日：1994-04-27

申请号：EP93308259.6

申请日：1993-10-18

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Poterek, Thomas J. ,  Broseghini, James L.

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

摘要： A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the re-stacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.

摘要翻译： 一种用于拆垛的方法和装置中的数据处理系统（100）寄存器的值。 在一种形式中，本发明是中断处理过程中的数据处理系统（100）中的更多的时间有效的解决方案，以拆垛和堆叠寄存器（154-158）的问题的。 通过取factthat的优点拉动的寄存器值从堆栈的不改变任何保存在所有正被用作堆栈存储器中的值的，本发明减少了卸垛每次堆叠没两个中断处理回 到后端之间没有非中断处理。 本发明消除了程序计数器寄存器（158），并通过没有任何相应的堆叠卸堆或操作改变堆栈指针寄存器（161）的值的寄存器的重新堆叠（154-158）的卸垛。

公开(公告)号：EP0576841A2

公开(公告)日：1994-01-05

申请号：EP93108749.8

申请日：1993-06-01

申请人： MOTOROLA, INC.

发明人： Bettelheim, Rudolf ,  Amedeo, Robert J. ,  Langan, John A.

IPC分类号： G04F10/04

CPC分类号： G06F1/14

摘要： A digital timer apparatus (10) incorporates a free running counter (12), an interval timer (18), a capture register (14), a pulse accumulator (20) and holding logic (16, 22). A rising or falling edge of an external signal causes the current contents of the free running counter (12) to be loaded into the capture register (14) and causes the pulse accumulator (20) to be incremented. The output of the interval timer (18) can cause the contents of the pulse accumulator (20) and capture register (14) to be stored into the holding logic (16, 22). The timer apparatus (10) is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

摘要翻译： 数字定时器装置（10）包括自由运行计数器（12），间隔定时器（18），捕获寄存器（14），脉冲累加器（20）和保持逻辑（16,22）。 外部信号的上升沿或下降沿使得自由运行计数器（12）的当前内容被加载到捕捉寄存器（14）中，并使脉冲累加器（20）递增。 间隔定时器（18）的输出可以使脉冲累加器（20）和捕捉寄存器（14）的内容存储到保持逻辑（16,22）中。 定时器装置（10）特别适合于执行与确定旋转构件的旋转速度相关的任务，并且可以用于例如在防抱死制动系统中检测车轮转速或检测轴旋转 自动变速器的速度。

公开(公告)号：EP0594377B1

公开(公告)日：1999-06-09

申请号：EP93308259.6

申请日：1993-10-18

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Poterek, Thomas J. ,  Broseghini, James L.

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

公开(公告)号：EP0594969A1

公开(公告)日：1994-05-04

申请号：EP93113638.6

申请日：1993-08-26

申请人： MOTOROLA, INC.

发明人： Sibigtroth, James M. ,  Viot, J.Greg ,  Langan, John A. ,  Broseghini, James L.

IPC分类号： G06F9/355 ,  G06F7/50

CPC分类号： G06F7/505 ,  G06F9/322 ,  G06F9/355 ,  G06F2207/3832

摘要： A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

摘要翻译： 一种数据处理系统（10）执行索引寻址，自动增量，并且使用两个字节边界的功率autodecrementing。 例如，一个5位的偏移允许用户无论是通过数据的一个表向前或向后前进16个字节。 到指定手术的指令将被执行，指针寄存器（58，60），以及偏移值在执行单元（14）被提供给。 指针寄存器（58，60）存储第一地址值和所述偏移值具有符号和大小。 算术逻辑单元，ALU，（52）反转偏移值，以提供到反相符号值的符号。 加法器（100，102，104，106，和108）中的多个加偏移值，第一地址值，并且反转的符号值，以产生抵消总和。 正的偏移值是由一个增加的，以产生的两个偏移范围内的对称的功率。

公开(公告)号：EP0540949A2

公开(公告)日：1993-05-12

申请号：EP92118085.7

申请日：1992-10-22

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Amedeo, Robert J. ,  Frontera, Roberto M.

IPC分类号： G06F1/025 ,  G06F1/08 ,  G04F1/00 ,  H03K5/05

CPC分类号： G06F1/025

摘要： A data processing system (10) capable of generating an output waveform (22) that has enhanced pulse width resolution. In one form, the system uses a counter (34) which is incremented by an input clock (20) running at an operating frequency of the system. Instead of incrementing the counter (34) by one, the counter (34) is incremented by a power of two so that the counter (34) appears to be counting a power of two faster. However, in order to increase the effective resolution of the counter (34) , the second edge of the output waveform (22) must be correctly adjusted depending on the desired duty cycle and period. The end result is a counter (34) that can produce a power of two greater resolution while still using the operating frequency of the system as an input clock (20).

摘要翻译： 一种数据处理系统（10），其能够在输出波形（22）产生的并具有增强的脉冲宽度分辨率。 在一种形式中，该系统使用该被加至输入时钟（20）的计数器（34）所有在在该系统的工作频率运行，而是增加由一个计数器（34），计数器（34）被加 二的幂这样做的计数器（34）似乎是计数两个更快的功率。 然而，为了增加所述计数器（34）的有效分辨率，输出波形（22）的第二边缘必须正确取决于期望的占空比和周期调整。 最终的结果是一个计数器（34），确实可以产生两个更大的分辨率的能力，同时使用该系统的工作频率，以输入时钟（20）停止。

公开(公告)号：EP0594969B1

公开(公告)日：1999-05-19

申请号：EP93113638.6

申请日：1993-08-26

申请人： MOTOROLA, INC.

发明人： Sibigtroth, James M. ,  Viot, J.Greg ,  Langan, John A. ,  Broseghini, James L.

IPC分类号： G06F9/355 ,  G06F7/50

CPC分类号： G06F7/505 ,  G06F9/322 ,  G06F9/355 ,  G06F2207/3832

公开(公告)号：EP0576841A3

公开(公告)日：1996-03-20

申请号：EP93108749.8

申请日：1993-06-01

申请人： MOTOROLA, INC.

发明人： Bettelheim, Rudolf ,  Amedeo, Robert J. ,  Langan, John A.

IPC分类号： G04F10/04

CPC分类号： G06F1/14

摘要： A digital timer apparatus (10) incorporates a free running counter (12), an interval timer (18), a capture register (14), a pulse accumulator (20) and holding logic (16, 22). A rising or falling edge of an external signal causes the current contents of the free running counter (12) to be loaded into the capture register (14) and causes the pulse accumulator (20) to be incremented. The output of the interval timer (18) can cause the contents of the pulse accumulator (20) and capture register (14) to be stored into the holding logic (16, 22). The timer apparatus (10) is particularly well suited to performing tasks related to the determination of the speed of rotation of a rotating member and may be used, for instance, in detecting wheel rotational speeds in an anti-lock brake system or detecting shaft rotation speeds in an automatic transmission.

公开(公告)号：EP0594377A3

公开(公告)日：1994-09-28

申请号：EP93308259.6

申请日：1993-10-18

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Poterek, Thomas J. ,  Broseghini, James L.

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

摘要： A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the re-stacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.

公开(公告)号：EP0738975A1

公开(公告)日：1996-10-23

申请号：EP96105177.8

申请日：1996-04-01

申请人： MOTOROLA, INC.

发明人： Broseghini, James L. ,  Langan, John A. ,  Poterek, Thomas J.

IPC分类号： G06F11/273 ,  G06F11/267

CPC分类号： G01R31/318547 ,  G06F11/2236

摘要： A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.

摘要翻译： 数据处理器（12）具有用于扫描测试某些电路的内置电路。 数据处理器生成并将测试向量存储在通常用于数据和指令存储的存储器系统（22）中。 这些载体可以比任何扫描链的大小大得多。 在测试期间，存储的矢量被自动路由到要测试的电路（36,38），输出与基准相比较。 数据处理器（12）不需要暂停以产生附加的测试向量。 因此，数据处理器（12）可以使用单个电路来产生扫描数据并以最小的定时或尺寸影响来压缩扫描结果。