公开(公告)号：EP0594969A1

公开(公告)日：1994-05-04

申请号：EP93113638.6

申请日：1993-08-26

申请人： MOTOROLA, INC.

发明人： Sibigtroth, James M. ,  Viot, J.Greg ,  Langan, John A. ,  Broseghini, James L.

IPC分类号： G06F9/355 ,  G06F7/50

CPC分类号： G06F7/505 ,  G06F9/322 ,  G06F9/355 ,  G06F2207/3832

摘要： A data processing system (10) performs indexed addressing, autoincrementing, and autodecrementing using power of two byte boundaries. For example, a 5-bit offset allows a user to progress sixteen bytes either forward or backward through a table of data. An instruction specifying an operation to be performed, a pointer register (58, 60), and an offset value is provided to an execution unit (14). The pointer register (58, 60) stores a first address value and the offset value has a sign and a magnitude. An arithmetic logic unit, ALU, (52) inverts the sign of the offset value to provide an inverted sign value. A plurality of adders (100, 102, 104, 106, and 108) adds the offset value, the first address value, and the inverted sign value to generate an offset sum. A positive offset value is increased by one to generate a symmetric power of two offset range.

摘要翻译： 一种数据处理系统（10）执行索引寻址，自动增量，并且使用两个字节边界的功率autodecrementing。 例如，一个5位的偏移允许用户无论是通过数据的一个表向前或向后前进16个字节。 到指定手术的指令将被执行，指针寄存器（58，60），以及偏移值在执行单元（14）被提供给。 指针寄存器（58，60）存储第一地址值和所述偏移值具有符号和大小。 算术逻辑单元，ALU，（52）反转偏移值，以提供到反相符号值的符号。 加法器（100，102，104，106，和108）中的多个加偏移值，第一地址值，并且反转的符号值，以产生抵消总和。 正的偏移值是由一个增加的，以产生的两个偏移范围内的对称的功率。

公开(公告)号：EP0574713B1

公开(公告)日：1999-08-25

申请号：EP93107987.5

申请日：1993-05-17

申请人： MOTOROLA, INC.

发明人： Viot, Greg J. ,  Sibigtroth, James M. ,  Broseghini, James L.

IPC分类号： G06F7/48 ,  G06F7/60

CPC分类号： G06N7/04 ,  Y10S706/90

公开(公告)号：EP0594969B1

公开(公告)日：1999-05-19

申请号：EP93113638.6

申请日：1993-08-26

申请人： MOTOROLA, INC.

发明人： Sibigtroth, James M. ,  Viot, J.Greg ,  Langan, John A. ,  Broseghini, James L.

IPC分类号： G06F9/355 ,  G06F7/50

CPC分类号： G06F7/505 ,  G06F9/322 ,  G06F9/355 ,  G06F2207/3832

公开(公告)号：EP0574713A2

公开(公告)日：1993-12-22

申请号：EP93107987.5

申请日：1993-05-17

申请人： MOTOROLA, INC.

发明人： Viot, Greg J. ,  Sibigtroth, James M. ,  Broseghini, James L.

IPC分类号： G06F7/48 ,  G06F7/60

CPC分类号： G06N7/04 ,  Y10S706/90

摘要： A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

摘要翻译： 一种电路（14）响应于单个“REV”软件指令评估在数据处理器（10）的模糊逻辑规则复数。 REV指令的计算结果存储在存储器（32），以确定每个矿井的规则强度的规则。 来路从每个规则的后果由一个缓冲器地址分离。 为了评估来路，到ALU（52）先行词在从存储在累加器（58）的电流先行存储器（32）中减去。 随后，交换逻辑电路（46）提供控制信息来分配一个最小值作为该规则的规则强度。 同样，后果的评估过程中需要一个最大规则强度。 ALU（52）减去存储在累加器（58）的结果，在存储器（32）的结果。 取决于结果，交换逻辑电路（46）提供控制信息到一个最大规则强度指定给评估的规则的后果。

公开(公告)号：EP0668556A2

公开(公告)日：1995-08-23

申请号：EP95301153.3

申请日：1995-02-22

申请人： MOTOROLA, INC.

发明人： Winter, Marlan L. ,  Langan, John A. ,  Sibigtroth, James M.

IPC分类号： G06F13/16 ,  G06F5/06

CPC分类号： G06F5/065 ,  G06F13/1642

摘要： A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). Additionally, each peripheral device has a queue control register configured to access a selected channel of the queue memory. The queue memory system described herein efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. The queue memory system will wait for a timing cycle in which the central processing unit does not require use of a bus. At that time, the queue memory system will transfer data between the queue and a peripheral device.

摘要翻译： 队列存储器系统（10）提供了一种灵活的存储器传输系统，其使用单个事务来存储队列中的存储器值或从队列中检索存储器值。 队列控制器（20）控制队列存储器（18）和外围设备（22,24）之间的数据传输。 此外，每个外围设备具有配置成访问队列存储器的选定信道的队列控制寄存器。 本文描述的队列存储器系统有效地使用系统的中央处理单元（12）的周期时间来执行队列访问，而不会中断更一般的处理步骤。 队列存储器系统将等待中央处理单元不需要使用总线的定时周期。 此时，队列存储器系统将在队列和外围设备之间传输数据。

公开(公告)号：EP0574714A3

公开(公告)日：1994-10-12

申请号：EP93107988.3

申请日：1993-05-17

申请人： MOTOROLA, INC.

发明人： Viot, Greg J. ,  Sibigtroth, James M. ,  Broseghini, James L.

IPC分类号： G06F7/48 ,  G06F7/60

CPC分类号： G06N7/04 ,  Y10S706/90

摘要： A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

公开(公告)号：EP0574714A2

公开(公告)日：1993-12-22

申请号：EP93107988.3

申请日：1993-05-17

申请人： MOTOROLA, INC.

发明人： Viot, Greg J. ,  Sibigtroth, James M. ,  Broseghini, James L.

IPC分类号： G06F7/48 ,  G06F7/60

CPC分类号： G06N7/04 ,  Y10S706/90

摘要： A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

摘要翻译： 一种在模糊逻辑运算期间确定隶属集中的输入的隶属程度的电路（14）和方法。 隶属度由一个“MEM”软件指令计算。 MEM指令确定系统输入是否具有零度，饱和度级别或其间的一些值的隶属度。 操作数分配电路（50）和ALU（56）允许电路（14）更快地确定隶属度。 分配电路（50）基于要乘以的值中的有效位数来确定用于乘法运算的乘法器。 如果乘法器小于被乘数，则可以执行较短的乘法运算。 此外，ALU（56）以分割操作模式操作，其能够同时执行两个8位减法或乘法运算，这也导致这些操作更有效地执行。

公开(公告)号：EP0668556A3

公开(公告)日：1995-12-06

申请号：EP95301153.3

申请日：1995-02-22

申请人： MOTOROLA, INC.

发明人： Winter, Marlan L. ,  Langan, John A. ,  Sibigtroth, James M.

IPC分类号： G06F13/16 ,  G06F5/06

CPC分类号： G06F5/065 ,  G06F13/1642

摘要： A queue memory system (10) provides a flexible memory transfer system which uses a single transaction to either store a memory value in a queue or to retrieve the memory value from the queue. A queue controller (20) controls the transfer of data between a queue memory (18) and the peripheral devices (22, 24). Additionally, each peripheral device has a queue control register configured to access a selected channel of the queue memory. The queue memory system described herein efficiently uses the cycle time of a central processing unit (12) of the system to perform queue accesses without disrupting more general processing steps. The queue memory system will wait for a timing cycle in which the central processing unit does not require use of a bus. At that time, the queue memory system will transfer data between the queue and a peripheral device.

公开(公告)号：EP0655678A1

公开(公告)日：1995-05-31

申请号：EP94117498.9

申请日：1994-11-07

申请人： MOTOROLA, INC.

发明人： Sibigtroth, James M. ,  Viot, Greg J. ,  Winter, Marlan L.

IPC分类号： G06F9/38 ,  G06F9/302

CPC分类号： G06F9/3001 ,  G06F9/325 ,  G06F9/3861

摘要： The data processing system(10) implements a resumable instruction using two instruction bytes. When a program counter (72) points to a first instruction byte, a first data processing operation is initiated. If an interrupt occurs during execution of the first data processing operation, intermediate data calculations held in a plurality of temporary registers (64, 66, 68) are saved in stack memory at a location pointed to by the stack pointer register (72). The program counter is incremented to point to a second byte of the instruction. An instruction resume operation is executed and the intermediate results of the data processing operation are accessed from the stack memory and restored to respective storage locations within the data processing system. After the intermediate results are restored, the program counter is decremented to point to the first instruction byte and the instruction continues executing the data processing operation as though no interrupt occurred.

摘要翻译： 数据处理系统（10）使用两个指令字节实现可恢复指令。 当程序计数器（72）指向第一个指令字节时，启动第一个数据处理操作。 如果在执行第一数据处理操作期间发生中断，则保持在多个临时寄存器（64,66,68）中的中间数据计算在堆栈指针寄存器（72）所指向的位置处被保存在堆栈存储器中。 程序计数器递增以指向指令的第二个字节。 执行指令恢复操作，并且从堆栈存储器访问数据处理操作的中间结果并将其恢复到数据处理系统内的各个存储位置。 中间结果恢复后，程序计数器递减以指向第一个指令字节，指令继续执行数据处理操作，就像没有发生中断一样。

公开(公告)号：EP0574713A3

公开(公告)日：1994-04-20

申请号：EP93107987.5

申请日：1993-05-17

申请人： MOTOROLA, INC.

发明人： Viot, Greg J. ,  Sibigtroth, James M. ,  Broseghini, James L.

IPC分类号： G06F7/48 ,  G06F7/60

CPC分类号： G06N7/04 ,  Y10S706/90

摘要： A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

摘要翻译： 响应于单个“REV”软件指令评估数据处理器（10）中的多个模糊逻辑规则的电路（14）。 REV指令评估存储在存储器（32）中的规则以确定每个规则的强度。 前件通过缓冲地址与每个规则的后果分开。 为了评估先行词，ALU（52）从存储在累加器（58）中的当前先行词中减去存储器（32）中的先行词。 随后，交换逻辑（46）提供控制信息以分配最小值作为规则的规则强度。 同样，在评估后果时需要最大的规则强度。 ALU（52）从存储在累加器（58）中的结果中减去存储器（32）中的结果。 取决于结果，交换逻辑（46）提供控制信息来为评估规则的后果分配最大规则强度。