Disclosed is a memory cell array (10) including: word lines (WL) and first and second bit lines (BL1,BL2) respectively connected to memory cells (100), wherein each memory cell (100) includes a MOS transistor (110) and a nanogap element (120) formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to a selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells.