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    Memory cell array comprising nanogap memory elements
    6.
    发明公开
    Memory cell array comprising nanogap memory elements 有权
    包含纳米间隙存储器元件的存储器单元阵列

    公开(公告)号：EP2202799A3

    公开(公告)日：2013-09-04

    申请号：EP09179363.8

    申请日：2009-12-16

    申请人： Funai Electric Co., Ltd. ,  Funai Electric Advanced Applied Technology Research Institute Inc.

    发明人： Takahashi, Tsuyoshi ,  Furuta, Shigeo ,  Masuda, Yuichiro ,  Ono, Masatoshi

    IPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/02

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array (10) including: word lines (WL) and first and second bit lines (BL1,BL2) respectively connected to memory cells (100), wherein each memory cell (100) includes a MOS transistor (110) and a nanogap element (120) formed inside a contact hole, the switching element includes first and second conductive layers and a gap in which a resistance value is changed by applying a predetermined voltage, each word line is connected to a gate electrode, each first bit line is connected to a second electrode, each second bit line is connected to the second conductive layer, and data is written by supplying a write voltage to the first bit line connected to a selected memory cell and specifying the word line connected to the memory cell, and data is read by supplying a read voltage to the first bit lines connected to the memory cell and specifying the word line connected to the memory cells.

    摘要翻译： 公开了一种存储器单元阵列（10），包括：分别连接到存储器单元（100）的字线（WL）和第一和第二位线（BL1，BL2），其中每个存储器单元（100）包括MOS晶体管（110） 和形成在接触孔内的纳米间隙元件（120），所述开关元件包括第一导电层和第二导电层以及通过施加预定电压而改变电阻值的间隙，每个字线连接到栅电极，每个第一 位线连接到第二电极，每个第二位线连接到第二导电层，并且通过向与所选存储器单元连接的第一位线提供写入电压并且指定连接到存储器的字线来写入数据 通过向连接到存储单元的第一位线提供读电压并指定连接到存储单元的字线来读取数据。

    Memory cell array comprising nanogap memory elements
    7.
    发明公开
    Memory cell array comprising nanogap memory elements 有权
    包含纳米间隙存储器元件的存储器单元阵列

    公开(公告)号：EP2202797A2

    公开(公告)日：2010-06-30

    申请号：EP09179361.2

    申请日：2009-12-16

    申请人： Funai Electric Advanced Applied Technology Research Institute Inc. ,  Funai Electric Co., Ltd.

    发明人： Takahashi, Tsuyoshi ,  Hayashi, Yutaka ,  Masuda, Yuichiro ,  Furuta, Shigeo ,  Ono, Masatoshi

    IPC分类号： H01L27/24 ,  G11C13/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array (10) including word lines (WL), first bit lines (BL1) and second bit lines (BL2) respectively connected to memory cells (100), wherein each memory cell (100) includes a MOS transistor (110) and a nanogap element (120) having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to a sense amplifier (51), specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了包括分别连接到存储单元（100）的字线（WL），第一位线（BL1）和第二位线（BL2）的存储单元阵列（10），其中每个存储单元（100）包括MOS晶体管 110）和纳米间隙元件（120），所述纳米间隙元件（120）具有第一导电层和第二导电层以及通过施加预定电压而电阻值改变的间隙，并且通过指定第一位线来写入数据以将其连接到地， 并向第二位线提供写入电压，并且通过指定第一位线来读取它以将其连接到读出放大器（51），指定字线并将低于写入电压的读取电压提供给第二位线 并且当字线电压变为栅极阈值电压或更大以及驱动电压和栅极阈值电压之和或更小时指定字线。