发明公开
EP2976770A1 PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS
有权
在数据访问之前静态随机存取存储器（SRAM）中的预充电二线以降低泄漏功率，以及相关的系统和方法
- 专利标题： PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS
- 专利标题（中）： 在数据访问之前静态随机存取存储器（SRAM）中的预充电二线以降低泄漏功率，以及相关的系统和方法
-
申请号： EP14727682.8申请日： 2014-05-02
-
公开(公告)号： EP2976770A1公开(公告)日： 2016-01-27
- 发明人: CHAI, Chiaming , GE, Shaoping , LILES, Stephen, Edward , GARG, Kunal
- 申请人： Qualcomm Incorporated
- 申请人地址： 5775 Morehouse Drive San Diego, CA 92121 US
- 专利权人： Qualcomm Incorporated
- 当前专利权人： Qualcomm Incorporated
- 当前专利权人地址： 5775 Morehouse Drive San Diego, CA 92121 US
- 代理机构： Skrba, Sinéad
- 优先权： US201361819744P 20130506; US201314049312 20131009
- 国际公布： WO2014182554 20141113
- 主分类号： G11C11/412
- IPC分类号： G11C11/412 ; G11C11/413 ; G11C7/12 ; G11C7/10
摘要：
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.
公开/授权文献
信息查询
