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    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS
    1.
    发明公开
    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS 有权
    在数据访问之前静态随机存取存储器（SRAM）中的预充电二线以降低泄漏功率，以及相关的系统和方法

    公开(公告)号：EP2976770A1

    公开(公告)日：2016-01-27

    申请号：EP14727682.8

    申请日：2014-05-02

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward ,  GARG, Kunal

    IPC分类号： G11C11/412 ,  G11C11/413 ,  G11C7/12 ,  G11C7/10

    CPC分类号： G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

    摘要： Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

    摘要翻译： 这里公开的实施例包括用于在数据访问之前对静态随机存取存储器（SRAM）中的位线进行预充电以减少泄漏功率的方法和设备。 存储器访问逻辑电路接收包括要在SRAM的SRAM数据阵列的第一数据存取路径中存取的数据入口地址的存储器存取请求。 SRAM还包括设置在第一数据存取路径外的第二数据存取路径中的预充电电路。 预充电电路被配置为使能SRAM存储器访问请求的一部分的SRAM数据阵列的预充电，以避免在空闲期间预充电SRAM数据阵列中的位线以减少泄漏功率。 预充电电路可以在数据访问之前启用对SRAM数据阵列的预充电，使得预充电电路不向第一数据存取路径增加等待时间。

    REDIRECTING DATA FROM A DEFECTIVE DATA ENTRY IN MEMORY TO A REDUNDANT DATA ENTRY PRIOR TO DATA ACCESS, AND RELATED SYSTEMS AND METHODS
    2.
    发明公开
    REDIRECTING DATA FROM A DEFECTIVE DATA ENTRY IN MEMORY TO A REDUNDANT DATA ENTRY PRIOR TO DATA ACCESS, AND RELATED SYSTEMS AND METHODS 审中-公开
    数据转移与商店一个错误的数据录入冗余信息项的数据访问之前和相关系统和方法

    公开(公告)号：EP2994914A1

    公开(公告)日：2016-03-16

    申请号：EP14730305.1

    申请日：2014-05-06

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward

    IPC分类号： G11C29/00

    摘要： Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

    LOGIC STATE CATCHING CIRCUITS
    4.
    发明公开
    LOGIC STATE CATCHING CIRCUITS 审中-公开
    LOGIKZUSTAND-FANGSCHALTUNGEN

    公开(公告)号：EP2186196A1

    公开(公告)日：2010-05-19

    申请号：EP08781030.5

    申请日：2008-06-26

    申请人： QUALCOMM Incorporated

    发明人： GE, Shaoping ,  CHAI, Chiaming ,  FISCHER, Jeffrey Herbert

    IPC分类号： H03K5/1534 ,  G01R29/027

    CPC分类号： H03K5/1534 ,  H03K19/19

    摘要： A number of logic state catching circuits (200) are described which use a logic circuit (204) with a first input (210), a second input, (232) and an output. The logic circuit (204) is configured to respond to a change in state of a data value coupled to the first input (210) causing a representative value of the data „ value to be generated on the output(212). The second input (232) receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element (206) is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input (232). A reset element (208) is configured to respond to a change in state of a clock input (230)by resetting the latching element. (206)

    A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH
    7.
    发明公开
    A PULSE CLOCK GENERATION LOGIC WITH BUILT-IN LEVEL SHIFTER AND PROGRAMMABLE RISING EDGE AND PULSE WIDTH 有权
    具有集成幻灯片，可编程上升沿和脉冲宽度脉冲时钟产生逻辑电平

    公开(公告)号：EP2831694A1

    公开(公告)日：2015-02-04

    申请号：EP13715579.2

    申请日：2013-03-28

    申请人： Qualcomm Incorporated

    发明人： GE, Shaoping ,  CHAI, Chiaming ,  LILES, Stephen Edward ,  NGUYEN, Lam V. ,  FISCHER, Jeffrey Herbert

    IPC分类号： G06F1/04 ,  G11C7/22 ,  G11C11/419

    CPC分类号： G06F1/04 ,  G11C7/222 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    摘要： Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit (100) includes a selective delay logic (102) to provide a programmable rising edge delay of the pulse clock (114), a selective pulse width widening logic (110) to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

    摘要翻译： 系统和用于产生脉冲的时钟具有可编程边缘并且被配置用于改变不同的存储器存取操作的要求的脉冲宽度的方法。 脉冲时钟生成电路包括一选择性延迟逻辑，用于提供所述脉冲时钟的可编程上升沿延迟，一个选择脉冲宽度加宽逻辑，以提供所述脉冲时钟的可编程脉冲宽度，和一个内置的电平移位器用于转换电压 脉冲时钟的水平。 对于读手术的上升沿延迟被编程以在预期readArray接入延迟对应，以及用于操作的写入脉冲宽度被编程比用于读操作的脉冲宽度得以体现。