公开(公告)号：EP4116976B1

公开(公告)日：2024-08-28

申请号：EP22183496.3

申请日：2022-07-07

IPC分类号： G11C7/04 ,  G11C7/10 ,  G11C7/12 ,  G11C11/419 ,  G11C7/06

CPC分类号： G11C7/1006 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/12 ,  G11C11/419 ,  G11C7/062 ,  G11C7/067

公开(公告)号：EP4398250A1

公开(公告)日：2024-07-10

申请号：EP24150148.5

申请日：2024-01-03

申请人： Samsung Electronics Co., Ltd.

发明人： YOON, Jayang ,  KIM, Chihyun ,  NAM, Sangwan ,  YOON, Chiweon ,  CHOI, Hyeongdo

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/30 ,  G11C16/12

CPC分类号： G11C7/12 ,  G11C5/147 ,  G11C8/08 ,  G11C16/30 ,  G11C16/12

摘要： Disclosed is a memory device in which at least one word line or bit line is charged by a plurality of charging terminals. The memory device includes a first charging terminal for supplying a first voltage to the at least one word line or bit line, and a second charging terminal for suppling a second voltage to the at least one word line or bit line when voltage supply by the first charging terminal is completed. The supply of the second voltage starts when a charged voltage of the at least one word line or bit line, charged by using the first voltage, satisfies a first reference condition.

公开(公告)号：EP4210060B1

公开(公告)日：2024-07-03

申请号：EP22152221.2

申请日：2022-01-19

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C7/18 ,  G11C5/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

CPC分类号： G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10 ,  G11C7/18 ,  G11C7/12 ,  G11C5/066 ,  G11C7/1084 ,  Y02D10/00

公开(公告)号：EP4354436A1

公开(公告)日：2024-04-17

申请号：EP23187989.1

申请日：2023-07-27

申请人： GlobalFoundries U.S. Inc.

发明人： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC分类号： G11C7/10 ,  G06F7/544 ,  G06N3/065 ,  G11C7/12 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C27/02

CPC分类号： G11C7/1006 ,  G06F7/5443 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C7/1084 ,  G11C7/12 ,  G11C27/026 ,  G11C2213/7720130101 ,  G11C7/1039

摘要： A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：EP4300497A1

公开(公告)日：2024-01-03

申请号：EP23163785.1

申请日：2023-03-23

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Taeyun

IPC分类号： G11C7/12 ,  G11C16/24

摘要： A nonvolatile memory device is provided. The nonvolatile memory device includes: a bitline; a precharge transistor configured to electrically connect the bitline to a power supply voltage during a precharge period of a read operation to transmit a bitline current flowing from the power supply voltage to the bitline; a cell string connected between the bitline and a source line, the cell string including a plurality of memory cells and being configured to transmit a first portion of the bitline current as a cell current; and a current control switch circuit connected between the bitline and a sink node, the current control switch circuit being configured to transmit a second portion of the bitline current as a control current flowing from the bitline to the sink node during the precharge period.

公开(公告)号：EP4293671A1

公开(公告)日：2023-12-20

申请号：EP23174857.5

申请日：2023-05-23

申请人： STMicroelectronics International N.V.

发明人： RAWAT, Harsh ,  DHORI, Kedar Janardan ,  KUMAR, Promod ,  CHAWLA, Nitin ,  AYODHYAWASI, Manuj

IPC分类号： G11C7/10 ,  G06N3/063 ,  G11C7/12

摘要： An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：EP3769307B1

公开(公告)日：2023-11-08

申请号：EP19771178.1

申请日：2019-01-28

发明人： TIWARI, Vipin ,  TRAN, Hieu, Van ,  DO, Nhan ,  REITEN, Mark

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C8/10 ,  G11C16/32 ,  H10B41/35 ,  H10B41/40

公开(公告)号：EP3329490B1

公开(公告)日：2023-04-05

申请号：EP16831256.9

申请日：2016-07-26

发明人： HUFFMAN, David A.

IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/06 ,  G11C7/12

公开(公告)号：EP4136537A1

公开(公告)日：2023-02-22

申请号：EP21722737.0

申请日：2021-04-14

申请人： Advanced Micro Devices, Inc.

发明人： NAG, Anirban ,  JAYASENA, Nuwan ,  AGA, Shaizeen

IPC分类号： G06F13/16 ,  G11C7/12

公开(公告)号：EP4116977A1

公开(公告)日：2023-01-11

申请号：EP22182472.5

申请日：2022-07-01

申请人： STMicroelectronics International N.V.

发明人： RAWAT, Harsh ,  DHORI, Kedar Janardan ,  KUMAR, Promod ,  CHAWLA, Nitin ,  AYODHYAWASI, Manuj

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/418 ,  G11C11/419 ,  G11C8/08

摘要： A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a second voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a first voltage level (greater than the second voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.