包括高压MOS晶体管，HV，和至少一个电容器，CAPA，其中集成电路：在HV晶体管的栅极堆叠（11）包括第一绝缘层（5,7）靠在 半导体层（1）并涂有第一多晶硅（9）; CAPA电容器包括在所述第一多晶硅的第一电极（13），并且在第二多晶硅在第一电极上休息至少部分的第二电极（25）（23），绝缘体（15，17，19） 从半导体层和第一电极分离第二电极; 第一氧化硅间隔物（39）横向地界定HV晶体管的第二电极（25）和栅极叠层（11）; 和第二氮化硅间隔物（41）排列第一间隔物（39）。

An integrated circuit comprising a high voltage MOS transistor, HV, and at least one capacitor, CAPA, wherein:
the gate stack (11) of the HV transistor comprises a first insulating layer (5, 7) resting on a semiconductor layer (1) and coated with a first polycrystalline silicon (9);
CAPA capacitor comprises a first electrode (13) in the first polycrystalline silicon, and a second electrode (25) in a second polysilicon (23) resting at least partially on the first electrode, an insulator (15, 17, 19) separating the second electrode of the semiconductor layer and the first electrode;
first spacers of silicon oxide (39) laterally bordering the second electrode (25) and the gate stack (11) of the HV transistor; and
second spacers of silicon nitride (41) bordering the first spacers (39).