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公开(公告)号：EP3809455A1
公开(公告)日：2021-04-21
申请号：EP20200176.4
申请日：2020-10-06
IPC分类号： H01L21/762 , H01L27/105 , H01L27/11541
摘要： Le procédé de fabrication de circuit intégré comprend une phase de formation de tranchées comprenant :
- une formation d'une première couche d'arrêt (20) ;
- une formation d'une deuxième couche d'arrêt (30) sur la première couche d'arrêt (20) dans une deuxième zone (Z2) seulement ;
- une gravure sèche (400) configurée pour graver en un temps donné la première couche d'arrêt (20) puis au moins une première tranchée (410) dans le substrat (10) jusqu'à une première profondeur (P1), et pour graver en même temps dans la deuxième zone (Z2), la deuxième couche d'arrêt (30), puis la première couche d'arrêt (20), puis au moins une deuxième tranchée (420) dans le substrat (10) jusqu'à une deuxième profondeur (P2), la deuxième profondeur (P2) étant inférieure à la première profondeur (P1).-
公开(公告)号：EP3188234B1
公开(公告)日：2020-10-21
申请号：EP16166144.2
申请日：2016-04-20
IPC分类号： H01L27/06 , H01L27/11546 , H01L29/66 , H01L21/28 , H01L49/02 , H01L29/49 , H01L21/8234 , H01L27/11541
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公开(公告)号：EP3965157A1
公开(公告)日：2022-03-09
申请号：EP21202902.9
申请日：2018-06-08
发明人： WANG, Yigong
IPC分类号： H01L27/11521 , H01L27/11558 , H01L27/11541 , H01L27/11543
摘要： Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.
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公开(公告)号：EP3203501A2
公开(公告)日：2017-08-09
申请号：EP17152661.9
申请日：2017-01-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： SONG, Changgeng
IPC分类号： H01L21/28 , H01L29/423 , H01L21/764 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543
CPC分类号： H01L27/11543 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/0657 , H01L29/42324 , H01L29/4234 , H01L29/4991
摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate electrode layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate electrode layer, the gate dielectric layer, the charge storage layer using the patterned metal gate electrode layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate electrode layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.
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5.发明公开
公开(公告)号：EP3416191A3
公开(公告)日：2019-02-20
申请号：EP18176686.6
申请日：2018-06-08
发明人： Wang, Yigong
IPC分类号： H01L27/11521 , H01L27/11558 , H01L27/11541 , H01L27/11543
摘要： Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.
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公开(公告)号：EP3203501A3
公开(公告)日：2017-11-01
申请号：EP17152661.9
申请日：2017-01-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： SONG, Changgeng
IPC分类号： H01L21/28 , H01L29/423 , H01L21/764 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543
CPC分类号： H01L27/11543 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/0657 , H01L29/42324 , H01L29/4234 , H01L29/4991
摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate electrode layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate electrode layer, the gate dielectric layer, the charge storage layer using the patterned metal gate electrode layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate electrode layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.
摘要翻译： 一种用于制造半导体器件的方法包括提供具有依次形成在有源区上的有源区，栅极绝缘层，电荷存储层，栅极电介质层和栅电极层的衬底结构。 该方法还包括在衬底结构上形成图案化的金属层，使用图案化的金属栅电极层作为掩模去除栅电极层，栅极电介质层，电荷存储层的相应部分，以形成与 彼此靠一个空间。 每个栅极结构包括包含电荷存储层的第二部分，栅极电介质层，栅极电极层和栅极线之一的堆叠。 该方法进一步包括在拉伸该空间的栅极结构的表面上形成层间介电层，同时在该空间中形成气隙。
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公开(公告)号：EP3188234A1
公开(公告)日：2017-07-05
申请号：EP16166144.2
申请日：2016-04-20
IPC分类号： H01L27/06 , H01L27/11546 , H01L29/66 , H01L21/8234 , H01L27/11541
摘要： L'invention concerne un circuit intégré comprenant un transistor MOS haute tension, HV, et au moins un condensateur, CAPA, dans lequel :
l'empilement de grille (11) du transistor HV comporte une première couche isolante (5, 7) reposant sur une couche semiconductrice (1) et revêtue d'un premier silicium polycristallin (9) ;
le condensateur CAPA comporte une première électrode (13) en le premier silicium polycristallin, et une deuxième électrode (25) en un deuxième silicium polycristallin (23) reposant au moins en partie sur la première électrode, un isolant (15, 17, 19) séparant la deuxième électrode de la couche semiconductrice et de la première électrode ;
des premiers espaceurs en oxyde de silicium (39) bordent latéralement la deuxième électrode (25) et l'empilement de grille (11) du transistor HV ; et
des deuxièmes espaceurs en nitrure de silicium (41) bordent les premiers espaceurs (39).摘要翻译： 包括高压MOS晶体管，HV，和至少一个电容器，CAPA，其中集成电路：在HV晶体管的栅极堆叠（11）包括第一绝缘层（5,7）靠在 半导体层（1）并涂有第一多晶硅（9）; CAPA电容器包括在所述第一多晶硅的第一电极（13），并且在第二多晶硅在第一电极上休息至少部分的第二电极（25）（23），绝缘体（15，17，19） 从半导体层和第一电极分离第二电极; 第一氧化硅间隔物（39）横向地界定HV晶体管的第二电极（25）和栅极叠层（11）; 和第二氮化硅间隔物（41）排列第一间隔物（39）。
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