- 专利标题： A STANDARD CELL ARCHITECTURE FOR REDUCED LEAKAGE CURRENT AND IMPROVED DECOUPLING CAPACITANCE
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申请号： EP17745907.0申请日： 2017-07-12
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公开(公告)号： EP3485512A1公开(公告)日： 2019-05-22
- 发明人: SAHU, Satyanarayana , CHEN, Xiangdong , VILANGUDIPITCHAI, Ramaprasath , KUMAR, Dorav
- 申请人： Qualcomm Incorporated
- 申请人地址： 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 专利权人： Qualcomm Incorporated
- 当前专利权人： Qualcomm Incorporated
- 当前专利权人地址： 5775 Morehouse Drive San Diego, CA 92121-1714 US
- 代理机构： Schmidbauer, Andreas Konrad
- 优先权： US201615209650 20160713
- 国际公布： WO2018013695 20180118
- 主分类号： H01L27/02
- IPC分类号： H01L27/02 ; H01L27/118 ; H01L27/092 ; H03K19/177 ; H03K19/00 ; H03K19/003
摘要：
A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
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