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1.发明授权
公开(公告)号：EP3485512B1
公开(公告)日：2020-01-08
申请号：EP17745907.0
申请日：2017-07-12
IPC分类号： H01L27/02 , H01L27/118 , H01L27/092 , H03K19/177 , H03K19/00 , H03K19/003 , H01L29/94
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公开(公告)号：EP3262759A1
公开(公告)日：2018-01-03
申请号：EP16702861.2
申请日：2016-01-19
发明人： VILANGUDIPITCHAI, Ramaprasath , KUMAR, Dorav , DILLEN, Steven James , KWON, Ohsang , JAFFARI, Javid
CPC分类号： H03K17/04206 , H03K5/24 , H03K5/26 , H03K19/0016
摘要： Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.
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3.发明公开
公开(公告)号：EP3475981A1
公开(公告)日：2019-05-01
申请号：EP17722594.3
申请日：2017-04-26
发明人： KUMAR, Dorav , NARAYANAN, Venkatasubramanian , THALLA, Bala Krishna , RASOULI, Seid Hadi , GUTTAL, Radhika Vinayak , PATURI, Sivakumar
IPC分类号： H01L23/528 , H03K19/177
摘要： A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.
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公开(公告)号：EP3545553A1
公开(公告)日：2019-10-02
申请号：EP17783677.2
申请日：2017-09-28
IPC分类号： H01L27/02 , H01L23/522 , H01L27/06 , H01L29/94
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公开(公告)号：EP3912011A1
公开(公告)日：2021-11-24
申请号：EP19828116.4
申请日：2019-12-05
发明人： SRINIVAS, Raghavendra , MUDIGONDA, Uday Shankar , SAMSON, Giby , VILANGUDIPITCHAI, Ramaprasath , KUMAR, Dorav
IPC分类号： G06F1/3287 , H03K17/16 , H03K17/284 , H03K19/00
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6.发明授权
公开(公告)号：EP3475981B1
公开(公告)日：2019-12-11
申请号：EP17722594.3
申请日：2017-04-26
发明人： KUMAR, Dorav , NARAYANAN, Venkatasubramanian , THALLA, Bala Krishna , RASOULI, Seid Hadi , GUTTAL, Radhika Vinayak , PATURI, Sivakumar
IPC分类号： H01L23/528 , H03K19/177 , H01L27/02 , H01L27/088 , H03K19/003
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7.发明公开
公开(公告)号：EP3552204A1
公开(公告)日：2019-10-16
申请号：EP17801561.6
申请日：2017-11-06
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8.发明公开
公开(公告)号：EP3485512A1
公开(公告)日：2019-05-22
申请号：EP17745907.0
申请日：2017-07-12
IPC分类号： H01L27/02 , H01L27/118 , H01L27/092 , H03K19/177 , H03K19/00 , H03K19/003
摘要： A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
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