发明公开
- 专利标题: MULTICHIP PACKAGE LINK
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申请号: EP20206632.0申请日: 2016-02-22
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公开(公告)号: EP3846042A1公开(公告)日: 2021-07-07
- 发明人: WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , BIRRITTELLA, Mark S. , AGARWAL, Ishwar , TEH, Lip Khoon , LIM, Su Wei , UPADHYAY, Anoop Kumar
- 申请人: INTEL Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Blvd.
- 代理机构: Samson & Partner Patentanwälte mbB
- 优先权: US201514669975 20150326
- 主分类号: G06F13/42
- IPC分类号: G06F13/42 ; G06F13/14 ; H04L12/701 ; G06F13/36 ; G06F13/40
摘要:
The present disclosure provides an integrated circuit die. The integrated circuit die comprising a hard IP (HIP) subassembly comprising a plurality of hard logic blocks, a hard logic block associated with a plurality of data lanes. The plurality of data lanes having separate per-lane enables. The integrated circuit die comprising a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols. The plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate data in accordance with a second data communication protocol. The integrated circuit die comprising a soft IP (SIP) assembly having at least one soft logic block comprising routable logic to selectively map a data lane of the plurality of data lanes to the first protocol-specific logic block and a data lane of the plurality of data lanes to the second protocol-specific logic block.
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