公开(公告)号：EP3284089A1

公开(公告)日：2018-02-21

申请号：EP16780406.1

申请日：2016-02-10

申请人： INTEL Corporation

发明人： DUDULWAR, Pankaj Vinayak ,  BANDI, Chenchu Punnarao ,  TEH, Lip Khoon ,  TAN, Tat Hin

IPC分类号： G11C7/06 ,  G11C5/14

CPC分类号： H04L7/0037 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C11/165 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0812 ,  H04L27/0002

摘要： Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.

公开(公告)号：EP3846042A1

公开(公告)日：2021-07-07

申请号：EP20206632.0

申请日：2016-02-22

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701 ,  G06F13/36 ,  G06F13/40

摘要： The present disclosure provides an integrated circuit die. The integrated circuit die comprising a hard IP (HIP) subassembly comprising a plurality of hard logic blocks, a hard logic block associated with a plurality of data lanes. The plurality of data lanes having separate per-lane enables. The integrated circuit die comprising a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols. The plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate data in accordance with a second data communication protocol. The integrated circuit die comprising a soft IP (SIP) assembly having at least one soft logic block comprising routable logic to selectively map a data lane of the plurality of data lanes to the first protocol-specific logic block and a data lane of the plurality of data lanes to the second protocol-specific logic block.

公开(公告)号：EP3796181A1

公开(公告)日：2021-03-24

申请号：EP20206623.9

申请日：2016-02-22

申请人： INTEL Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701 ,  G06F13/36 ,  G06F13/40

摘要： The present disclosure provides a multi-chip package comprising a substrate, a first integrated circuit (IC) die packaged onto the substrate and a second IC die packaged onto the substrate and connected to the first IC die using a multi-chip package link (MCPL). The MCPL including an upstream channel and a downstream channel each associated with a set of lanes. The first IC die comprising a CPU and an interface to connect the CPU. The interface including a physical layer (PHY) to provide a physical connection over which data is communicated between the first IC die and the second IC die. The PHY comprising a transmitter to transmit data to the second IC die, a receiver to receive data from the second IC die and a clock recovery circuit to center a clock signal in both the time domain and the voltage domain and to receive a clock signal from the second IC die over a strobe lane. To center in the time domain, the clock recovery circuit is to determine a phase of the clock signal and to adjust the phase of the clock signal. To center in the voltage domain, the clock recovery circuit is to adjust a reference voltage. The clock recovery circuit to sample data signals in accordance with the reference voltage and the clock signal using a plurality of data samplers for each lane.

公开(公告)号：EP3274857A1

公开(公告)日：2018-01-31

申请号：EP16769240.9

申请日：2016-02-22

申请人： Intel Corporation

发明人： WAGH, Mahesh ,  WU, Zuoguo ,  IYER, Venkatraman ,  PASDAST, Gerald S. ,  BIRRITTELLA, Mark S. ,  AGARWAL, Ishwar ,  TEH, Lip Khoon ,  LIM, Su Wei ,  UPADHYAY, Anoop Kumar

IPC分类号： G06F13/42 ,  G06F13/14 ,  H04L12/701

CPC分类号： G06F13/4022 ,  G06F13/36 ,  G06F13/4068

摘要： A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.