发明公开

MULTICHIP PACKAGE LINK
摘要:
The present disclosure provides an integrated circuit die. The integrated circuit die comprising a hard IP (HIP) subassembly comprising a plurality of hard logic blocks, a hard logic block associated with a plurality of data lanes. The plurality of data lanes having separate per-lane enables. The integrated circuit die comprising a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols. The plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate data in accordance with a second data communication protocol. The integrated circuit die comprising a soft IP (SIP) assembly having at least one soft logic block comprising routable logic to selectively map a data lane of the plurality of data lanes to the first protocol-specific logic block and a data lane of the plurality of data lanes to the second protocol-specific logic block.
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