Invention Grant
- Patent Title: Planar heterogeneous device
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Application No.: US15026271Application Date: 2013-12-18
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Publication No.: US10014374B2Publication Date: 2018-07-03
- Inventor: Kimin Jun , Patrick Morrow
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- International Application: PCT/US2013/076058 WO 20131218
- International Announcement: WO2015/094219 WO 20150625
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/10 ; H01L29/78 ; H01L21/8258 ; H01L21/02 ; H01L21/8234 ; H01L27/092 ; H01L29/16 ; H01L29/20 ; H01L29/22 ; H01L29/267 ; H01L21/762

Abstract:
In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is patterned into desired wells. Between the wells, the first layer is exposed. The exposed first layer is epitaxially grown to the level of the transferred second layer to complete a planar heterogeneous substrate including both S1 and S2. The heterogeneous materials may be utilized such that, for example, a P channel device formed from one of III-V or IV materials is coplanar with an N channel device formed from one of III-V or IV materials. The embodiment requires no lattice parameter compliance due to the second layer being transferred onto the first layer. Also, there is no (or little) buffer and/or hetero-epitaxy. Other embodiments are described herein.
Public/Granted literature
- US20160247882A1 PLANAR HETEROGENEOUS DEVICE Public/Granted day:2016-08-25
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