A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M−1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.