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    Non-volatile boolean logic operation circuit and operation method thereof
    2.
    发明授权
    Non-volatile boolean logic operation circuit and operation method thereof 有权
    非易失性布尔逻辑运算电路及其运算方法

    公开(公告)号：US09473137B2

    公开(公告)日：2016-10-18

    申请号：US14867030

    申请日：2015-09-28

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui Miao ,  Yaxiong Zhou ,  Yi Li ,  Huajun Sun

    IPC: H03K19/00 ,  H03K19/20 ,  H03K19/08

    CPC classification number: H03K19/0002 ,  H03K19/0021 ,  H03K19/0813 ,  H03K19/20

    Abstract: A non-volatile Boolean logic operation circuit, including: two input ends; an output end; a first resistive switching element M1, the first resistive switching element M including a positive electrode and a negative electrode; and a second resistive switching element M2, the second resistive switching element M2 including a positive electrode and a negative electrode. The negative electrode of the first resistive switching element M1 operates as a first input end of the logic operation circuit. The negative electrode of the second resistive switching element M2 operates as a second input end of the logic operation circuit. The positive electrode of the second resistive switching element M2 is connected to the positive electrode of the first resistive switching element M1, and a connected end thereof operates as the output end of the logic operation circuit.

    Abstract translation: 一种非易失性布尔逻辑运算电路，包括：两个输入端; 输出端 第一电阻式开关元件M1，第一电阻式开关元件M包括正极和负极; 和第二电阻开关元件M2，第二电阻开关元件M2包括正极和负极。 第一电阻式开关元件M1的负电极作为逻辑运算电路的第一输入端工作。 第二电阻开关元件M2的负极作为逻辑运算电路的第二输入端工作。 第二电阻开关元件M2的正极与第一电阻式开关元件M1的正极连接，其连接端作为逻辑运算电路的输出端。

    Memory-based convolutional neural network system
    3.
    发明授权
    Memory-based convolutional neural network system 有权

    公开(公告)号：US11531880B2

    公开(公告)日：2022-12-20

    申请号：US16464977

    申请日：2018-06-07

    Applicant: Huazhong University of Science and Technology

    Inventor： Yi Li ,  Wenqian Pan ,  Xiangshui Miao

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

    Abstract: A memory-based CNN, includes an input module, a convolution layer circuit module, a pooling layer circuit module, an activation function module, a fully connected layer circuit module, a softmax function module and an output module, convolution kernel values or synapse weights are stored in the NOR FLASH units; the input module converts an input signal into a voltage signal required by the convolutional neural network; the convolutional layer circuit module convolves the voltage signal corresponding to the input signal with the convolution kernel values, and transmits the result to the activation function module; the activation function module activates the signal; the pooling layer circuit module performs a pooling operation on the activated signal; the fully connected layer circuit module multiplies the pooled signal with the synapse weights to achieve classification; the softmax function module normalizes the classification result into probability values as an output of the entire network.

    Computing array based on 1T1R device, operation circuits and operating methods thereof
    4.
    发明授权
    Computing array based on 1T1R device, operation circuits and operating methods thereof 有权

    公开(公告)号：US11475949B2

    公开(公告)日：2022-10-18

    申请号：US16336900

    申请日：2018-06-07

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi Li ,  Zhuorui Wang ,  Xiangshui Miao ,  Yaxiong Zhou ,  Long Cheng

    IPC: G11C11/00 ,  G11C13/00 ,  G06F7/48 ,  H03K19/21

    Abstract: The present invention discloses a computing array based on 1T1R device, operation circuits and operating methods thereof. The computing array has 1T1R arrays and a peripheral circuit; the 1T1R array is configured to achieve operation and storage of an operation result, and the peripheral circuit is configured to transmit data and control signals to control operation and storage processes of the 1T1R arrays; the operation circuits are respectively configured to implement a 1-bit full adder, a multi-bit step-by-step carry adder and optimization design thereof, a 2-bit data selector, a multi-bit carry select adder and a multi-bit pre-calculation adder; and in the operating method corresponding to the operation circuit, initialized resistance states of the 1T1R devices, word line input signals, bit line input signals and source line input signals are controlled to complete corresponding operation and storage processes.

    Max pooling processor based on 1T1R memory
    5.
    发明授权
    Max pooling processor based on 1T1R memory 有权

    公开(公告)号：US11416744B2

    公开(公告)日：2022-08-16

    申请号：US16631840

    申请日：2019-07-12

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi Li ,  Rui Kuang ,  Xiang-Shui Miao

    IPC: G11C11/54 ,  G06N3/08 ,  G06N3/04 ,  G11C13/00

    Abstract: The present disclosure belongs to the technical field of artificial neural networks, and provides to a max pooling processor based on 1T1R memory, comprising an input module, a max pooling operation module, and an output module; the input module is configured to transmit an operating voltage according to the convolution result in the convolutional neural network; the 1T1R memory in the max pooling operation module is configured to adjust a conductance value of the RRAM according to the gate voltage of the transistor therein to achieve the max pooling operation by using the non-volatile multi-value conductance regulation characteristic of the RRAM, and store a max pooling result; and the output module is configured to read the max pooling result and output it.

    Associative memory circuit
    6.
    发明授权
    Associative memory circuit 有权
    关联存储器电路

    公开(公告)号：US09564218B2

    公开(公告)日：2017-02-07

    申请号：US14601216

    申请日：2015-01-20

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui Miao ,  Yi Li ,  Lei Xu ,  Yingpeng Zhong

    IPC: G11C15/04 ,  G11C11/54 ,  G11C13/00

    CPC classification number: G11C15/046 ,  G11C11/54 ,  G11C13/0007

    Abstract: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.

    Abstract translation: 一种包括第一忆阻器，第二忆阻器，固定值电阻器R和操作比较器的关联存储器电路。 第一忆阻器的一个端子是相关存储器电路的第一输入端，并且第一忆阻器的另一端连接到操作比较器的第一输入端。 第二忆阻器的一个端子是关联存储器电路的第二输入端，并且第二忆阻器的另一端连接到运算比较器的第一输入端。 固定值电阻的一端连接到运算比较器的第一输入端，固定值电阻的另一端连接到地。 操作比较器的第二输入端连接到参考电压。

    Nonvolatile logic gate circuit based on phase change memory
    7.
    发明授权
    Nonvolatile logic gate circuit based on phase change memory 有权
    基于相变存储器的非易失逻辑门电路

    公开(公告)号：US09369130B2

    公开(公告)日：2016-06-14

    申请号：US14706004

    申请日：2015-05-07

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui Miao ,  Yi Li ,  Yingpeng Zhong ,  Lei Xu ,  Huajun Sun ,  Xiaomin Cheng

    IPC: H03K19/003 ,  G11C13/00 ,  H03K19/173 ,  H03K19/20 ,  H03K19/177

    CPC classification number: H03K19/00346 ,  G11C13/0004 ,  G11C13/004 ,  H03K19/1733 ,  H03K19/17724 ,  H03K19/20

    Abstract: A nonvolatile logic gate circuit based on phase change memories, including a first phase change memory, a second phase change memory, a first controllable switch element and a first resistor, wherein a first end of the first phase change memory serves as a first input end of an AND gate circuit, a first end of the second phase change memory serves as a second input end of the AND gate circuit, a first end of the first controllable switch element is connected to a second end of the first phase change memory, a second end of the first controllable switch element is grounded; one end of the first resistor is connected to the first end of the second phase change memory, the other end of the first resistor is grounded; and the first end of the second phase change memory serves as an output end of the AND gate circuit.

    Abstract translation: 一种基于相变存储器的非易失性逻辑门电路，包括第一相变存储器，第二相变存储器，第一可控开关元件和第一电阻器，其中第一相变存储器的第一端用作第一输入端 和门电路的第一端，第二相变存储器的第一端用作与门电路的第二输入端，第一可控开关元件的第一端连接到第一相变存储器的第二端， 第一可控开关元件的第二端接地; 第一电阻器的一端连接到第二相变存储器的第一端，第一电阻器的另一端接地; 并且第二相变存储器的第一端用作与门电路的输出端。

    Convolutional neural network on-chip learning system based on non-volatile memory
    8.
    发明授权
    Convolutional neural network on-chip learning system based on non-volatile memory 有权

    公开(公告)号：US11861489B2

    公开(公告)日：2024-01-02

    申请号：US16961932

    申请日：2019-07-12

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Xiangshui Miao ,  Yi Li ,  Wenqian Pan

    IPC: G06N3/065 ,  G06N3/04 ,  G06N3/08 ,  G06F17/15

    CPC classification number: G06N3/065 ,  G06F17/153 ,  G06N3/04 ,  G06N3/08

    Abstract: Disclosed by the disclosure is a convolutional neural network on-chip learning system based on non-volatile memory, comprising: an input module, a convolutional neural network module, an output module and a weight update module. The on-chip learning of the convolutional neural network module implements the synaptic function by using the characteristic of the memristor, and the convolutional kernel value or synaptic weight value is stored in a memristor unit; the input module converts the input signal into the voltage signal; the convolutional neural network module converts the input voltage signal layer-by-layer, and transmits the result to the output module to obtain the output of the network; and the weight update module adjusts the conductance value of the memristor in the convolutional neural network module according to the result of the output module to update the network convolutional kernel value or synaptic weight value.

    Non-volatile logic device based on phase-change magnetic materials and logic operation method thereof
    9.
    发明授权
    Non-volatile logic device based on phase-change magnetic materials and logic operation method thereof 有权
    基于相变磁性材料的非易失性逻辑器件及其逻辑运算方法

    公开(公告)号：US09543955B2

    公开(公告)日：2017-01-10

    申请号：US14849621

    申请日：2015-09-10

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiangshui Miao ,  Yi Li ,  Yingpeng Zhong

    IPC: H03K19/08 ,  G11C11/16 ,  G11C13/00 ,  H03K19/177 ,  G11B5/02 ,  H03K19/18

    CPC classification number: H03K19/08 ,  G11B5/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0097 ,  H03K19/1776 ,  H03K19/18

    Abstract: A non-volatile logic device, including: a substrate, a magnetic head, a base electrode, an insulating layer, a phase-change magnetic film, and a top electrode. The substrate includes a silicon substrate and an active layer attached to the silicon substrate. The base electrode includes an N-type silicon layer, a P-type silicon layer and a heating layer, the N-type silicon layer and the P-type silicon layer constitute a PN diode structure, and the size of the heating layer is smaller than that of the P-type silicon layer. The phase-change magnetic film is deposited on the insulating layer and is electrically contacted with the heating layer. The top electrode and the base electrode are connected to an external electrical pulse signal, and an external magnetic field parallel to a two dimensional plane of the phase-change magnetic film is applied to the non-volatile logic device.

    Abstract translation: 一种非易失性逻辑器件，包括：基板，磁头，基极，绝缘层，相变磁性膜和顶部电极。 衬底包括硅衬底和附着到硅衬底的有源层。 基极包括N型硅层，P型硅层和加热层，N型硅层和P型硅层构成PN二极管结构，加热层的尺寸较小 比P型硅层高。 相变磁性膜沉积在绝缘层上并与加热层电接触。 顶部电极和基极连接到外部电脉冲信号，并且将平行于相变磁性膜的二维平面的外部磁场施加到非易失性逻辑器件。

    Preparation method of bipolar gating memristor and bipolar gating memristor
    10.
    发明授权
    Preparation method of bipolar gating memristor and bipolar gating memristor 有权

    公开(公告)号：US11825756B2

    公开(公告)日：2023-11-21

    申请号：US17785916

    申请日：2021-08-30

    Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

    Inventor： Yi Li ,  Yuhui He ,  Yaoyao Fu ,  Xiaodi Huang ,  Xiangshui Miao

    IPC: H10N70/00 ,  H10N70/20 ,  H10B63/00

    CPC classification number: H10N70/826 ,  H10B63/22 ,  H10B63/84 ,  H10N70/026 ,  H10N70/245

    Abstract: The present invention provides a preparation method of a bipolar gating memristor and a bipolar gating memristor. The preparation method includes: preparing a lower electrode; depositing a resistive material layer on the lower electrode; and depositing an upper electrode on the resistive material layer by using a magnetron sputtering manner to deposit the upper electrode, controlling upper electrode metal particles to have suitable kinetic energy by controlling sputtering power, controlling a vacuum degree of a region where the upper electrode and the resistive material layer are located, such that a redox reaction occurs spontaneously between the upper electrode and the resistive material layer during the deposition of the upper electrode to form a built-in bipolar gating layer; and continuously depositing the upper electrode on the built-in bipolar gating layer.

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