Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage capacitor having a first node coupled with the first complementary bit line, and a transistor selectable by a word line to couple a second node of the storage capacitor to the first bit line, wherein a voltage potential across the first bit line and the first complementary bit line when the transistor is selected is indicative of a bit of data.