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1.发明公开公开(公告)号：US20240204792A1
公开(公告)日：2024-06-20
申请号：US18085094
申请日：2022-12-20
发明人： Chia-Yu CHEN , Ankur Agrawal , Andrea Fasoli , Kyu-hyoun Kim
IPC分类号： H03M1/38
CPC分类号： H03M1/38
摘要： An apparatus includes multiple analog to digital converters. Individual analog to digital converters are configured to produce a digital output from an analog input and configured to compute a least significant bit of the digital output by comparing an internal residual voltage for determination of the least significant bit and a residual voltage from another analog to digital converter.
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公开(公告)号：US11593196B2
公开(公告)日：2023-02-28
申请号：US17539813
申请日：2021-12-01
摘要： A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
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公开(公告)号：US20210318852A1
公开(公告)日：2021-10-14
申请号：US16847505
申请日：2020-04-13
发明人： Seyoung Kim , Mingu Kang , Kyu-hyoun Kim , Seonghoon Woo
摘要： A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
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4.发明申请公开(公告)号：US20210208847A1
公开(公告)日：2021-07-08
申请号：US16737440
申请日：2020-01-08
发明人： Mingu Kang , Seyoung Kim , Kyu-hyoun Kim , Eun Kyung Lee
摘要： A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.
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公开(公告)号：US10546628B2
公开(公告)日：2020-01-28
申请号：US15860871
申请日：2018-01-03
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , G11C11/4076 , G11C11/24 , G11C11/4093 , G11C29/00 , G11C16/04 , G11C29/04 , G11C5/04
摘要： A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.
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公开(公告)号：US10255986B2
公开(公告)日：2019-04-09
申请号：US15617158
申请日：2017-06-08
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , Kyu-hyoun Kim , Anil B. Lingambudi , Adam J. McPadden
摘要： The present invention provides a computer implemented method, system, and computer program product of assessing in-field reliability of computer memories. In an embodiment, the present invention includes taking control of a portion of a computer memory circuit, utilizing a portion of a computer memory bus associated with the portion of the computer memory circuit, moving computer memory circuit data stored in the portion of the computer memory circuit to a host computer storage device, executing a set of logical operations assessing reliability of the portion of the computer memory circuit, resulting in assessment data stored in a reliability error monitor (REM) computer storage device, transmitting the stored assessment data from the REM computer storage device to a computer memory controller circuit, and in response to the transmitting, moving the moved computer memory circuit data from the host computer storage device back to the portion of the computer memory circuit.
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公开(公告)号：US20190033952A1
公开(公告)日：2019-01-31
申请号：US15684332
申请日：2017-08-23
摘要： A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.
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公开(公告)号：US10168922B1
公开(公告)日：2019-01-01
申请号：US15138610
申请日：2016-04-26
IPC分类号： G06F3/06 , G11C11/4096 , G11C11/406 , G11C11/20 , G11C14/00 , G06F11/20
摘要： An aspect includes data backup management between volatile memory and non-volatile memory in a through-silicon via module of a computer system. Data is copied data from the volatile memory to the non-volatile memory during a refresh cycle of the volatile memory. The data is written to one or more non-volatile memory cells within the non-volatile memory prior to a next refresh cycle of the volatile memory.
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公开(公告)号：US10063263B2
公开(公告)日：2018-08-28
申请号：US14717254
申请日：2015-05-20
发明人： Michael B. Healy , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Warren E. Maule , Adam J. McPadden
CPC分类号： H03M13/618 , G06F11/1016
摘要： A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ECC) bits and an extended correction table. The extended correction table stores error information additional to the ECC bits for one or more of the data in the memory array. The system also includes a controller to control the memory device to write and read the data.
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公开(公告)号：US10032505B2
公开(公告)日：2018-07-24
申请号：US14797993
申请日：2015-07-13
IPC分类号： G11C11/24 , G11C11/4096 , G11C11/4091 , G11C7/06 , G11C11/404 , G11C11/4097
CPC分类号： G11C11/4096 , G11C7/062 , G11C11/404 , G11C11/4091 , G11C11/4097 , G11C2207/002
摘要： Techniques are disclosed for dynamic random access memory (DRAM) cell. The DRAM cell comprises a first bit line and a first complementary bit line, a storage capacitor having a first node coupled with the first complementary bit line, and a transistor selectable by a word line to couple a second node of the storage capacitor to the first bit line, wherein a voltage potential across the first bit line and the first complementary bit line when the transistor is selected is indicative of a bit of data.
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