Invention Grant
- Patent Title: Method and device for testing a chain of flip-flops
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Application No.: US15244586Application Date: 2016-08-23
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Publication No.: US10048317B2Publication Date: 2018-08-14
- Inventor: Sylvain Clerc , Gilles Gasiot
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Crowe & Dunlevy
- Priority: FR1650947 20160205
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317

Abstract:
A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
Public/Granted literature
- US20170227602A1 METHOD AND DEVICE FOR TESTING A CHAIN OF FLIP-FLOPS Public/Granted day:2017-08-10
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