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公开(公告)号：US11131782B2
公开(公告)日：2021-09-28
申请号：US16677005
申请日：2019-11-07
发明人： Gilles Gasiot , Fady Abouzeid
IPC分类号： G01T1/24 , H01L27/07 , H01L31/103
摘要： A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.
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公开(公告)号：US20170227602A1
公开(公告)日：2017-08-10
申请号：US15244586
申请日：2016-08-23
发明人： Sylvain Clerc , Gilles Gasiot
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31723 , G01R31/31727 , G01R31/318392 , G01R31/318566
摘要： A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
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公开(公告)号：US11789168B2
公开(公告)日：2023-10-17
申请号：US17408679
申请日：2021-08-23
发明人： Gilles Gasiot , Fady Abouzeid
IPC分类号： G01T1/24 , H01L27/07 , H01L31/103
CPC分类号： G01T1/248 , G01T1/247 , H01L27/0761 , H01L31/103
摘要： A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation.
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公开(公告)号：US10684326B2
公开(公告)日：2020-06-16
申请号：US16031395
申请日：2018-07-10
发明人： Sylvain Clerc , Gilles Gasiot
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/3183 , G01R31/317
摘要： A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
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公开(公告)号：US10048317B2
公开(公告)日：2018-08-14
申请号：US15244586
申请日：2016-08-23
发明人： Sylvain Clerc , Gilles Gasiot
IPC分类号： G01R31/3177 , G01R31/317
摘要： A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
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公开(公告)号：US20180062652A1
公开(公告)日：2018-03-01
申请号：US15443779
申请日：2017-02-27
发明人： Fady Abouzeid , Gilles Gasiot
IPC分类号： H03K19/003 , H03K3/356
摘要： A storage element including two CMOS inverters, coupled head-to-tail between two nodes; and one MOS transistor, connected as a capacitor between said nodes.
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公开(公告)号：US11730433B2
公开(公告)日：2023-08-22
申请号：US17529543
申请日：2021-11-18
CPC分类号： A61B6/4208 , G01T1/24
摘要： An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.
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公开(公告)号：US10771048B2
公开(公告)日：2020-09-08
申请号：US16747341
申请日：2020-01-20
发明人： Capucine Lecat-Mathieu De Boissac , Fady Abouzeid , Gilles Gasiot , Philippe Roche , Victor Malherbe
摘要： A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
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公开(公告)号：US20180321308A1
公开(公告)日：2018-11-08
申请号：US16031395
申请日：2018-07-10
发明人： Sylvain Clerc , Gilles Gasiot
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/31723 , G01R31/31727 , G01R31/318392 , G01R31/318566
摘要： A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
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公开(公告)号：US20140340133A1
公开(公告)日：2014-11-20
申请号：US14276567
申请日：2014-05-13
IPC分类号： H03K19/003 , H03L7/08
CPC分类号： H03K19/0033 , G11C5/005 , H03K3/0375 , H03K3/356121 , H03L7/08 , H03L7/0891 , H03L7/0896 , H03L7/095 , H03L7/18
摘要： A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.
摘要翻译： 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。
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