Invention Grant
- Patent Title: Package structure to enhance yield of TMI interconnections
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Application No.: US15478064Application Date: 2017-04-03
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Publication No.: US10049971B2Publication Date: 2018-08-14
- Inventor: Thomas J. De Bonis , Lilia May , Rajen S. Sidhu , Mukul P. Renavikar , Ashay A. Dani , Edward R. Prack , Carl L. Deppisch , Anna M. Prakash , James C. Matayabas , Jason Jieping Zhang , Srinivasa R. Aravamudhan , Chang Lin
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/498 ; H01L25/065 ; H01L23/31 ; H01L25/10 ; H01L21/48 ; H01L21/56 ; H01L21/768 ; H01L25/00 ; H01L23/00

Abstract:
An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
Public/Granted literature
- US20170207152A1 Package Structure To Enhance Yield of TMI Interconnections Public/Granted day:2017-07-20
Information query
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