Invention Grant
- Patent Title: Tapered gate oxide in LDMOS devices
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Application No.: US14585933Application Date: 2014-12-30
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Publication No.: US10050115B2Publication Date: 2018-08-14
- Inventor: Brennan J. Brown , Natalie B. Feilchenfeld , Max G. Levy , Santosh Sharma , Yun Shi , Michael J. Zierak
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Michael LeStrange; Andrew M. Calderon
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L29/423
Abstract:
Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.
Public/Granted literature
- US20160190269A1 TAPERED GATE OXIDE IN LDMOS DEVICES Public/Granted day:2016-06-30
Information query
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