公开(公告)号：US09236449B2

公开(公告)日：2016-01-12

申请号：US13939231

申请日：2013-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Theodore J. Letavic ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/808 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/735

CPC classification number: H01L29/66681 ,  H01L29/1045 ,  H01L29/1058 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7818 ,  H01L29/7835

Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.

Abstract translation: 公开了具有电压线性化场板的高压LDMOS器件和制造方法。 该方法包括在深阱区域和衬底的主体上形成连续的栅极结构。 该方法还包括在连续栅极结构中形成相对掺杂的交替的段。 该方法还包括形成与连续栅极结构的尖端电连接的触点和形成在衬底中的漏极区。 该方法还包括形成与至少一种相反掺杂的交替区段的区段直接电接触的金属区域。

公开(公告)号：US08981475B2

公开(公告)日：2015-03-17

申请号：US13920236

申请日：2013-06-18

Applicant: International Business Machines Corporation

Inventor： Santosh Sharma ,  Yun Shi ,  Anthony K. Stamper

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/404 ,  H01L29/66681

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.

Abstract translation: 横向扩散金属氧化物半导体（LDMOS）包括在衬底的顶表面中具有STI结构的半导体衬底，STI结构下方的漂移区域，以及STI结构的相对侧上的源极区域和漏极区域。 栅极导体在STI结构和源极区之间的间隙上在衬底上，并且部分地与漂移区重叠。 保形介质层位于顶表面上，并在栅极导体上形成台面。 保形介电层具有嵌入其中的保形蚀刻停止层。 接触柱延伸穿过介电层和蚀刻停止层，并连接到源极区，漏极区和栅极导体。 源电极接触源极接触柱，栅电极接触栅接触柱，而漏电极接触漏接触柱。 漂移电极在漂移区域之上。

公开(公告)号：US08962402B1

公开(公告)日：2015-02-24

申请号：US13966312

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Santosh Sharma ,  Yun Shi ,  Anthony K. Stamper

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/404 ,  H01L29/0653 ,  H01L29/66681 ,  H01L29/7816

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region, and partially overlaps the drift region. Floating gate pieces are over the STI structure. A conformal dielectric layer is on the top surface and on the gate conductor and floating gate pieces and forms a mesa above the gate conductor and floating gate pieces. A conformal etch-stop layer is embedded within the conformal dielectric layer. A drift electrode is formed on the conformal etch-stop layer over, relative to the top surface, the drift region. The drift electrode has a variable thickness relative to the top surface.

Abstract translation: 横向扩散金属氧化物半导体（LDMOS）包括在衬底的顶表面中具有STI结构的半导体衬底，STI结构下方的漂移区域，以及STI结构的相对侧上的源极区域和漏极区域。 栅极导体在STI结构和源极区之间的间隙上在衬底上，并且部分地与漂移区重叠。 浮动门件超过了STI结构。 保形介质层位于顶表面上，栅极导体和浮栅上，并在栅极导体和浮栅上形成台面。 保形蚀刻停止层嵌入共形介电层内。 在保形蚀刻停止层上相对于顶表面漂移漂移区形成漂移电极。 漂移电极相对于顶表面具有可变的厚度。

公开(公告)号：US20150048447A1

公开(公告)日：2015-02-19

申请号：US13966312

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Santosh Sharma ,  Yun Shi ,  Anthony K. Stamper

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/404 ,  H01L29/0653 ,  H01L29/66681 ,  H01L29/7816

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region, and partially overlaps the drift region. Floating gate pieces are over the STI structure. A conformal dielectric layer is on the top surface and on the gate conductor and floating gate pieces and forms a mesa above the gate conductor and floating gate pieces. A conformal etch-stop layer is embedded within the conformal dielectric layer. A drift electrode is formed on the conformal etch-stop layer over, relative to the top surface, the drift region. The drift electrode has a variable thickness relative to the top surface.

Abstract translation: 横向扩散金属氧化物半导体（LDMOS）包括在衬底的顶表面中具有STI结构的半导体衬底，STI结构下方的漂移区域，以及STI结构的相对侧上的源极区域和漏极区域。 栅极导体在STI结构和源极区之间的间隙上在衬底上，并且部分地与漂移区重叠。 浮动门件超过了STI结构。 保形介质层位于顶表面上，栅极导体和浮栅上，并在栅极导体和浮栅上形成台面。 保形蚀刻停止层嵌入共形介电层内。 在保形蚀刻停止层上相对于顶表面漂移漂移区形成漂移电极。 漂移电极相对于顶表面具有可变的厚度。

公开(公告)号：US20140346596A1

公开(公告)日：2014-11-27

申请号：US13902245

申请日：2013-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Theodore J. Letavic ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L23/60 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.

Abstract translation: 公开了具有电压线性化场板的高压LDMOS器件和制造方法。 该方法包括通过对在深阱区域和衬底的主体上形成的多晶硅层进行构图来形成多岛阵列和控制栅极结构。 该方法还包括形成与控制栅极结构接触并且在多岛阵列上的金属屏蔽。

公开(公告)号：US20140367778A1

公开(公告)日：2014-12-18

申请号：US13920236

申请日：2013-06-18

Applicant: International Business Machines Corporation

Inventor： Santosh Sharma ,  Yun Shi ,  Anthony K. Stamper

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/404 ,  H01L29/66681

Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region and partially overlaps the drift region. A conformal dielectric layer is on the top surface and forms a mesa above the gate conductor. The conformal dielectric layer has a conformal etch-stop layer embedded therein. Contact studs extend through the dielectric layer and the etch-stop layer, and are connected to the source region, drain region, and gate conductor. A source electrode contacts the source contact stud, a gate electrode contacts the gate contact stud, and a drain electrode contacts the drain contact stud. A drift electrode is over the drift region.

Abstract translation: 横向扩散金属氧化物半导体（LDMOS）包括在衬底的顶表面中具有STI结构的半导体衬底，STI结构下方的漂移区域，以及STI结构的相对侧上的源极区域和漏极区域。 栅极导体在STI结构和源极区之间的间隙上在衬底上，并且部分地与漂移区重叠。 保形介质层位于顶表面上，并在栅极导体上形成台面。 保形介电层具有嵌入其中的保形蚀刻停止层。 接触柱延伸穿过介电层和蚀刻停止层，并连接到源极区，漏极区和栅极导体。 源电极接触源极接触柱，栅电极接触栅接触柱，而漏电极接触漏接触柱。 漂移电极在漂移区域之上。

公开(公告)号：US20140327084A1

公开(公告)日：2014-11-06

申请号：US13874922

申请日：2013-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; an shallow n-type well and a p-type well each within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well; and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括场效应晶体管（FET）结构和形成这种结构的方法。 在各种实施例中，FET结构包括：深n型阱; 深n型井内的浅n型井和p型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分; 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。

公开(公告)号：US09240463B2

公开(公告)日：2016-01-19

申请号：US13902245

申请日：2013-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Theodore J. Letavic ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66681 ,  H01L23/60 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1045 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an array of poly islands and a control gate structure by patterning a poly layer formed over a deep well region and a body of a substrate. The method further includes forming a metal shield in contact with the control gate structure and over the array of poly islands.

Abstract translation: 公开了具有电压线性化场板的高压LDMOS器件和制造方法。 该方法包括通过对在深阱区域和衬底的主体上形成的多晶硅层进行构图来形成多岛阵列和控制栅极结构。 该方法还包括形成与控制栅极结构接触并且在多岛阵列上的金属屏蔽。

公开(公告)号：US09224858B1

公开(公告)日：2015-12-29

申请号：US14445101

申请日：2014-07-29

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Santosh Sharma ,  Yun Shi ,  Anthony K. Stamper

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/7816 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66689

Abstract: Disclosed are a field effect transistor (FET) (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET)) and a method of forming the FET. In the FET, an etch stop pad is on a semiconductor substrate (e.g., a P-type silicon substrate). A semiconductor layer (e.g., a silicon layer) is also on the substrate and extends laterally over the etch stop pad. A first well region (e.g., an N-well region) extends through the semiconductor layer into the substrate such that it contains the etch stop pad. A second well region (e.g., a P-well region) is in the first well region aligned above the etch stop pad. A source region (e.g., a N-type source region) is in the second well region. A buried isolation region (e.g., a buried air-gap isolation region) is within the first well region aligned below the etch stop pad so as to limit vertical capacitor formation.

Abstract translation: 公开了场效应晶体管（FET）（例如，横向双扩散金属氧化物半导体场效应晶体管（LDMOSFET））和形成FET的方法。 在FET中，蚀刻停止焊盘位于半导体衬底（例如，P型硅衬底）上。 半导体层（例如，硅层）也在衬底上并横向延伸到蚀刻停止衬垫上。 第一阱区域（例如，N阱区域）穿过半导体层延伸到衬底中，使得其包含蚀刻停止焊盘。 第二阱区域（例如，P阱区域）位于蚀刻停止焊盘上方的第一阱区域中。 源极区域（例如，N型源极区域）位于第二阱区域中。 掩埋隔离区域（例如，埋入气隙隔离区域）位于蚀刻停止焊盘下方的第一阱区域内，以限制垂直电容器形成。

公开(公告)号：US20150255539A1

公开(公告)日：2015-09-10

申请号：US14712397

申请日：2015-05-14

Applicant: International Business Machines Corporation

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include field effect transistor (FET) structures and methods of forming such structures. In various embodiments, an FET structure includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括场效应晶体管（FET）结构和形成这种结构的方法。 在各种实施例中，FET结构包括：深n型阱; 深n型井内浅层n型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分， 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。