- Patent Title: Semiconductor device configured for avoiding electrical shorting
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Application No.: US14269566Application Date: 2014-05-05
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Publication No.: US10050118B2Publication Date: 2018-08-14
- Inventor: Ruilong Xie , Ryan Ryoung-han Kim , Chanro Park , William James Taylor, Jr. , John A. Iacoponi
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336 ; H01L29/06 ; H01L29/78

Abstract:
In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.
Public/Granted literature
- US20150318345A1 SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING Public/Granted day:2015-11-05
Information query
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