公开(公告)号：US20210043727A1

公开(公告)日：2021-02-11

申请号：US16534317

申请日：2019-08-07

申请人： GLOBALFOUNDRIES INC.

发明人： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

摘要： A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

摘要： Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10658243B2

公开(公告)日：2020-05-19

申请号：US16002385

申请日：2018-06-07

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Chanro Park

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L29/51

摘要： The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.

公开(公告)号：US20200152504A1

公开(公告)日：2020-05-14

申请号：US16185799

申请日：2018-11-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L29/49

摘要： Methods of forming a field-effect transistor and structures for a field effect-transistor. A sidewall spacer is formed adjacent to a sidewall of a gate structure of the field-effect transistor and a dielectric cap is formed over the gate structure and the sidewall spacer. A cut is formed that extends through the dielectric cap, the gate structure, and the sidewall spacer. After forming the cut, the sidewall spacer is removed from beneath the dielectric cap to define a cavity, and a dielectric material is deposited in the cut and in the cavity. The dielectric material encapsulates a portion of the cavity to define an airgap spacer.

公开(公告)号：US10566201B1

公开(公告)日：2020-02-18

申请号：US16174510

申请日：2018-10-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Ruilong Xie ,  Hui Zang ,  Laertis Economikos ,  Andre LaBonte

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66

摘要： A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

公开(公告)号：US10446653B2

公开(公告)日：2019-10-15

申请号：US15351893

申请日：2016-11-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Lars Wolfgang Liebmann ,  Hoon Kim

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/49 ,  H01L29/78 ,  H01L21/768

摘要： A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US10319627B2

公开(公告)日：2019-06-11

申请号：US15376831

申请日：2016-12-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L29/66

摘要： Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10243053B1

公开(公告)日：2019-03-26

申请号：US15876316

申请日：2018-01-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Andre Labonte ,  Chanro Park

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/417 ,  H01L21/28 ,  H01L23/528 ,  H01L29/78

摘要： One illustrative IC product disclosed herein includes a gate structure for a transistor, a conductive source/drain contact structure and an insulating source/drain cap structure positioned above the conductive source/drain contact structure, wherein the insulating source/drain cap structure has a first notch formed therein. In one illustrative example, the product also includes a sidewall spacer that has a second notch in an upper portion of the sidewall spacer, wherein a first portion of the insulating source/drain cap structure is positioned in the second notch, and a conductive gate contact structure comprising first and second portions, the first portion of the conductive gate contact structure being positioned in the first notch and the second portion of the conductive gate contact structure being in contact with the gate structure.

公开(公告)号：US10236291B2

公开(公告)日：2019-03-19

申请号：US15801023

申请日：2017-11-01

申请人： GLOBALFOUNDRIES INC.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/32 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

摘要： At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US10176996B2

公开(公告)日：2019-01-08

申请号：US14452606

申请日：2014-08-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/51

摘要： Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.