Invention Grant
- Patent Title: Method for late differential SOI thinning for improved FDSOI performance and HCI optimization
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Application No.: US15256027Application Date: 2016-09-02
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Publication No.: US10050119B2Publication Date: 2018-08-14
- Inventor: George Robert Mulfinger , Dina H. Triyoso , Ryan Sporer
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/66 ; H01L29/78 ; H01L29/772 ; H01L27/088 ; H01L21/324 ; H01L29/06 ; H01L29/417 ; H01L29/51 ; H01L21/84 ; H01L29/786

Abstract:
Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.
Public/Granted literature
- US20180069091A1 METHOD FOR LATE DIFFERENTIAL SOI THINNING FOR IMPROVED FDSOI PERFORMANCE AND HCI OPTIMIZATION Public/Granted day:2018-03-08
Information query
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