公开(公告)号：US09362284B2

公开(公告)日：2016-06-07

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L29/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US20150214322A1

公开(公告)日：2015-07-30

申请号：US14165209

申请日：2014-01-27

Applicant: Globalfoundries Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Robert Binder ,  Joachim Metzger ,  Patrick Polakowski

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/115

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/3105 ,  H01L27/11507 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.

Abstract translation: 本公开提供了一种半导体器件，其包括衬底，在衬底上形成的未掺杂的HfO 2层和形成在HfO 2层上的TiN层。 这里，未掺杂的HfO 2层至少部分是铁电的。 在用于形成半导体器件的说明性方法中，在半导体衬底上形成未掺杂的非晶HfO 2层，并且在未掺杂的非晶HfO 2层上形成TiN层。 进行热退火处理以至少部分地诱导未掺杂的无定形HfO 2层中的铁电相。

公开(公告)号：US10050119B2

公开(公告)日：2018-08-14

申请号：US15256027

申请日：2016-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Dina H. Triyoso ,  Ryan Sporer

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/772 ,  H01L27/088 ,  H01L21/324 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L21/84 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20180190768A1

公开(公告)日：2018-07-05

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76264 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/78684

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

公开(公告)号：US09583557B2

公开(公告)日：2017-02-28

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US20150364535A1

公开(公告)日：2015-12-17

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。

公开(公告)号：US09318315B2

公开(公告)日：2016-04-19

申请号：US14176208

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Mark Gerard Nolan ,  Wenke Weinreich ,  Konrad Seidel ,  Patrick Polakowski

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L21/02107 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/66181 ,  H01L29/94

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract translation: 本发明提供集成电路元件和具有高容量的集成电路元件和MIM / MIS电容器，以及集成电路元件和集成MIM / MIS电容器的形成方法以及控制集成电路元件和集成MIM / MIS电容器的方法。 在各个方面，提供基板，并且在基板上形成电介质层或绝缘层。 此外，在电介质层或绝缘层上设置电极层。 这里，电介质层或绝缘层处于反铁电相。 在各种示例性实施例中，集成电路元件可以实现MOSFET结构或电容器结构。

公开(公告)号：US20160064286A1

公开(公告)日：2016-03-03

申请号：US14476031

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gabriela Dilliway ,  Bo Bai ,  Peter Javorka ,  Dina H. Triyoso

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract translation: 提供了制造集成电路及其部件的方法。 根据示例性实施例，提供了一种用于制造集成电路的方法。 该方法包括在第一和第二栅极结构之外提供具有第一栅极结构和第二栅极结构以及浅沟槽隔离区域的半导体衬底，在第一栅极结构上沉积掩模，以及在浅沟槽上沉积保护层 隔离区域嵌入STI保护帽。

公开(公告)号：US20150014813A1

公开(公告)日：2015-01-15

申请号：US14176208

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Mark Gerard Nolan ,  Wenke Weinreich ,  Konrad Seidel ,  Patrick Polakowski

IPC: H01L49/02 ,  H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/66181 ,  H01L29/94

Abstract: The present disclosure provides integrated circuit elements and MIM/MIS capacitors having high capacitance and methods of forming according integrated circuit elements and integrated MIM/MIS capacitors and methods of controlling an integrated circuit element and an integrated MIM/MIS capacitor. In various aspects, a substrate is provided and a dielectric layer or insulating layer is formed over the substrate. Furthermore, an electrode layer is disposed over the dielectric layer or insulating layer. Herein, the dielectric layer or insulating layer is in an antiferroelectric phase. In various illustrative embodiments, the integrated circuit element may implement a MOSFET structure or a capacitor structure.

Abstract translation: 本发明提供集成电路元件和具有高容量的集成电路元件和MIM / MIS电容器，以及集成电路元件和集成MIM / MIS电容器的形成方法以及控制集成电路元件和集成MIM / MIS电容器的方法。 在各个方面，提供基板，并且在基板上形成电介质层或绝缘层。 此外，在电介质层或绝缘层上设置电极层。 这里，电介质层或绝缘层处于反铁电相。 在各种示例性实施例中，集成电路元件可以实现MOSFET结构或电容器结构。

公开(公告)号：US10236343B2

公开(公告)日：2019-03-19

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.