- 专利标题: Using the least significant bits of a called function's address to switch processor modes
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申请号: US13655499申请日: 2012-10-19
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公开(公告)号: US10055227B2公开(公告)日: 2018-08-21
- 发明人: Charles Joseph Tabony , Erich James Plondke , Lucian Codrescu , Suresh K. Venkumahanti , Evandro Carlos Menezes
- 申请人: QUALCOMM Incorporated
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 代理机构: Muncy, Geissler, Olds & Lowe, P.C.
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/38 ; G06F9/32
摘要:
Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.
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